FXLS8471Q datasheet(32/75 Pages) FREESCALE

32 / 75 page

FXLS8471Q

Sensors

Freescale Semiconductor, Inc.

10.1.7

WHO_AM_I (0x0D) register

Device identification register. This register contains the device identifier which is set to 0x6A.

10.1.8

CTRL_REG1 (0x2A) register

NOTE

Except for Standby mode selection, the device must be in Standby mode to change any of

the fields within CTRL_REG1 (0x2A).

It is important to note that when the device is in Auto-Sleep mode, the system ODR and data rate for all the system functional

blocks is overridden by the sleep data rate set by the aslp_rate field..

Table 31 shows the various system output data rates (ODR) that may be selected using the dr[2:0] bits.

Table 27. WHO_AM_I register

who_am_i[7:0]

0x6A

Table 28. CTRL_REG1 register

aslp_rate[1:0]

dr[2:0]

lnoise

f_read

active

3’b001

Table 29. CTRL_REG1 bit descriptions

Field

Description

aslp_rate[1:0]

Configures the auto-wake sample frequency when the device is in Sleep mode.

See Table 30 for more information.

dr[2:0]

Output Data Rate (ODR) selection.

See Table 31 for more information.

lnoise

Reduced noise and full-scale range mode (analog gain times 2).

0: Normal mode

1: Reduced noise mode; Note that the FSR setting is restricted to a ±4 g in this mode (lnoise = 1).

f_read

Fast-read mode: Data format is limited to the 8-bit MSB for accelerometer output data. The auto-address pointer will skip over

the LSB addresses for each axes sample data when performing a burst read operation.

0: Normal mode

1: Fast-read mode

active

Standby/Active.

0: Standby mode

1: Active mode

Table 30. Sleep mode poll rate description

aslp_rate1

aslp_rate0

Frequency (Hz)

12.5

6.25

1.56

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