PCM3168APAPR datasheet(27/66 Pages) TI1

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100

120

140

160

180

200

2.0

NormalizedFrequency(f )

0.5

1.0

1.5

DSM_Dual

DSM_Single

DF_Single

DF_Dual

100

120

140

160

180

200

2.0

NormalizedFrequency(f )

0.5

1.0

1.5

DSM_Dual

DSM_Single

DSM_Quad

DF_Dual

DF_Single

DF_Quad

PCM3168A

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SBAS452A – SEPTEMBER 2008 – REVISED JANUARY 2016

Table 5. DAC Digital Filter OSR, Modulator OSR, and Noise-Free Shaped Bandwidth

for Each Sampling Mode (continued)

NOISE-FREE SHAPED

BANDWIDTH

SAMPLING MODE

SYSTEM CLOCK

DIGITAL FILTER OSR

MODULATOR OSR

RATE (fS)

fS = 48

fS = 96

fS = 192

kHz

512, 768

N/A

x128

Single

256, 384

N/A

x128

128, 192(1)(2)

N/A

x64

256, 384

N/A

x64

Dual

128, 192(1)(2)

N/A

x64

Quad

128, 192(1)(2)

x32

spacer

Figure 37. ADC

ΔΣ Modulator and Digital Filter

Figure 38. DAC

ΔΣ Modulator and Digital Filter

Characteristic

9.3.6 Reset Operation

The PCM3168A device has both an internal power-on reset circuit and an external reset circuit. The sequences

for both reset circuits are illustrated in Figure 2, Timing Requirements: Power-On Reset, and Figure 39. Figure 2

and Timing Requirements: Power-On Reset describe the timing chart at the internal power-on reset. Initialization

is triggered automatically at the point where VDD exceeds 2.2 V typical, and the internal reset is released after

3846 SCKI clock cycles from power-on if RST is kept high and SCKI is provided. VOUT from the DACs are

forced to the VCOMDA level initially (0.5 × VCCDA1) and settles at a specified level according to the rising VCC.

If synchronization among SCKI, BCKAD/DA, and LRCKAD/DA is maintained, VOUT starts to output with a fade-

in sequence after tDACDLY1 from the internal reset release; VOUT then provides an output that corresponds to DIN

after (3846 SCKI + tDACDLY1 + tDACDLY2) from power-on. Meanwhile, DOUT from the ADCs begins to output with a

fade-in sequence after tADCDLY1 from the internal reset release; DOUT then provides output corresponding to VIN

after (3846 SCKI + tADCDLY1 + tADCDLY2) from power-on. If the synchronization is not held, the internal reset is not

released and both operating modes are maintained at reset and power-down states; after the synchronization

forms again, both the DAC and ADC return to normal operation with the above sequences.

Figure 39 illustrates a timing chart at the external reset. RST accepts an external forced reset by RST = low, and

provides a device reset and power-down state that makes the lowest power dissipation state available in the

PCM3168A device. If RST goes from high to low under synchronization among SCKI, BCKAD/DA, and

LRCKAD/DA, the internal reset is asserted, all registers and memory are reset, and finally the PCM3168A device

enters into an all power-down state. At the same time, VOUT is immediately forced into the AGNDDA1 level and

DOUT becomes 0. To begin normal operation again, toggle RST high; the same power-up sequence as power-

on reset shown in Figure 2 is performed.

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