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PCM3168APAPR Datasheet(PDF) 46 Page - Texas Instruments |
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PCM3168APAPR Datasheet(HTML) 46 Page - Texas Instruments |
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46 / 66 page ![]() PCM3168A SBAS452A – SEPTEMBER 2008 – REVISED JANUARY 2016 www.ti.com Table 22. Register: ADC Sampling Mode DEC HEX B7 B6 B5 B4 B3 B2 B1 B0 80 50 — — — — — — SRAD1 SRAD0 SRAD[1:0] ADC Sampling mode select These bits control the sampling mode of ADC operation. In Auto mode, the sampling mode is automatically set according to multiples between system clock and sampling clock, single rate for 512 fS and 768 fS, and dual rate for 256 fS and 384 fS. Default value: 00. SRAD ADC Sampling mode select 00 Auto (default) 01 Single rate 10 Dual rate 11 Reserved Table 23. Register: ADC Control 1 DEC HEX B7 B6 B5 B4 B3 B2 B1 B0 81 51 — MSAD2 MSAD1 MSAD0 — FMTAD2 FMTAD1 FMTAD0 MSAD[2:0] ADC Master/slave mode select These bits control the audio interface mode for ADC operation. Default value: 000 (slave mode). MSAD ADC Master/slave mode select 000 Slave mode (default) 001 Master mode, 768 fS 010 Master mode, 512 fS 011 Master mode, 384 fS 100 Master mode, 256 fS 101 Reserved 110 Reserved 111 Reserved FMTAD[2:0] ADC Audio interface format select These bits control the audio interface format for ADC operation. The format details and restrictions related to the system clock and master/slave mode are described in Audio Data Interface Formats and Timing. Default value: 000 (24-bit I2S format). FMTAD ADC Audio interface format select 000 24-bit I2S format (default) 001 24-bit left-justified format 010 24-bit right-justified format 011 16-bit right-justified format 100 24-bit I2S mode DSP format 101 24-bit left-justified mode DSP format 110 24-bit I2S mode TDM format 111 24-bit left-justified mode TDM format 46 Submit Documentation Feedback Copyright © 2008–2016, Texas Instruments Incorporated Product Folder Links: PCM3168A |
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