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PCM3168APAPR Datasheet(PDF) 31 Page - Texas Instruments

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Part # PCM3168APAPR
Description  Audio Codec
PDF  66 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

PCM3168APAPR Datasheet(HTML) 31 Page - Texas Instruments

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Transmitter
M
St
M
SlaveAddress
M
W
S
ACK
M
RegAddress
S
ACK
M
Sr
M
SlaveAddress
M
R
S
ACK
S
ReadData
M
NACK
M
Sp
DataType
PCM3168A
www.ti.com
SBAS452A – SEPTEMBER 2008 – REVISED JANUARY 2016
(1) M = Master device, S = Slave device, St = Start condition, Sr = Repeated start condition, W = Write, R = Read, ACK = Acknowledge,
NACK = Not acknowledge, and Sp = Stop condition.
NOTE: The slave address after the repeated start condition must be the same as the previous address.
Figure 46. Framework for Read Operation
9.4 Device Functional Modes
9.4.1 Mode Control
The PCM3168A device includes four-way mode control selectable by MODE pin, as shown in Table 6. The pull-
up and pull-down resistors must be 220 k
Ω ±5%. This mode control selection is sampled only when the internal
reset is released by a power-on reset or by a low-to-high transition of the external reset (RST pin); a system
clock is also required.
Table 6. Mode Control Selection
MODE
MODE CONTROL INTERFACE
Tied to DGND
Two-wire (I2C) serial control, selectable analog input configuration
Tied to DGND through pull-down resistor
H/W (hardware control), differential analog input
Tied to VDD through pull-up resistor
H/W (hardware control), single-ended analog input
Tied to VDD
Four-wire (SPI) serial control, selectable analog input configuration
From the mode control selection described in Table 6, the functions of four pins are changed, as shown in
Table 7.
Table 7. Pin Functions
PIN ASSIGNMENTS
PIN
SPI
I2C
H/W
MS/ADR0/MD0
MS
ADR0
MD0
MDO/ADR1/MD1
MDO
ADR1
MD1
MDI/SDA/DEMP
MDI
SDA
DEMP
MC/SCL/FMT
MC
SCL
FMT
Both serial controls are available while RST = high and after internal reset completion, which is indicated as a
negative transition (high
≥ low) of a 4096 × SCKI width pulse on the OVF pin.
9.4.2 Hardware Control Mode Configuration
The data format is selected by the MC/SCL/FMT pin between I2S format and I2S mode in TDM format, as shown
in Table 8.
Table 8. Data Format Selection
FMT
MODE CONTROL INTERFACE
Low
I2S audio data format
High
I2S mode, TDM audio data format (supported only for SCKI = 128 fS, 256 fS, or 512 fS)
Copyright © 2008–2016, Texas Instruments Incorporated
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Product Folder Links: PCM3168A



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