PCM3168APAPR datasheet(30/66 Pages) TI1

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Transmitter

DataType

SlaveAddress

ACK

RegAddress

ACK

WriteData1

ACK

WriteData2

ACK

SDA

SCL

SlaveAddress

R/W

(1)

ACK

(2)

DATA

(3)

ACK

DATA

ACK

1to7

1to8

ACK

Start

Condition

Stop

Condition

MSB

LSB

ADR1

ADR0

R/W

PCM3168A

SBAS452A – SEPTEMBER 2008 – REVISED JANUARY 2016

www.ti.com

9.3.14 Two-Wire (I2C) Serial Control

The PCM3168A device supports an I2C-compatible serial bus and data transmission protocol for fast mode

configured as a slave device. This protocol is explained in the I2C specification, version 2.0.

The PCM3168A device has a 7-bit slave address, as shown in Figure 43. The first five bits are the most

significant bits (MSB) of the slave address and are factory-preset to 10001. The next two bits of the address byte

are selectable bits that can be set by MS/ADR0/MD0 and MDO/ADR1/MD1. A maximum of four PCM3168A

device can be connected on the same bus at any one time. Each device responds when it receives its own slave

address.

Figure 43. Slave Address

9.3.15 Packet Protocol

A master device must control the packet protocol, which consists of the start condition, slave address with the

read/write bit, data if a write operation is required, acknowledgement if a read operation is required, and stop

condition. The PCM3168A device supports both slave receiver and transmitter functions. Details about DATA for

both write and read operations are described in Figure 44.

(1) R/W: Read operation if 1; write operation otherwise.

(2) ACK: Acknowledgement of a byte if 0, not Acknowledgement of a byite if 1.

(3) DATA: Eight bits (byte); details are described in the Write Operation and Read Operation sections.

Figure 44. DATA Operation

9.3.16 Write Operation

The PCM3168A device supports a receiver function. A master device can write to any PCM3168A device register

using single or multiple accesses. The master sends a PCM3168A device slave address with a write bit, a

by the data to be transferred. When the data are received properly, the index register is incremented by one

automatically. When the index register reaches 0x5E, the next value is 0x40. When undefined registers are

accessed, the PCM3168A device does not send an acknowledgment. Figure 45 illustrates a diagram of the write

operation. The register address and write data are in 8-bit, MSB-first format.

(1) M = Master device, S = Slave device, St = Start condition, W = Write, ACK = Acknowledge, and Sp = Stop condition.

Figure 45. Framework for Write Operation

9.3.17 Read Operation

A master device can read the registers from 0x40 to 0x5E of the PCM3168A device. The value of the register

address is stored in an indirect index register in advance. The master sends the PCM3168A slave address with a

read bit after storing the register address. Then the PCM3168A device transfers the data of the register with

address that is in the indirect index register. Figure 46 shows a diagram of the read operation.

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