PCM3168APAPR datasheet(49/66 Pages) TI1

49 / 66 page

PCM3168A

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SBAS452A – SEPTEMBER 2008 – REVISED JANUARY 2016

Table 28. Register: ADC Overflow Flag

DEC

HEX

—

OVF6

OVF5

OVF4

OVF3

OVF2

OVF1

OVF[6:1]

ADC Overflow flag (read-only)

These bits indicate the status information of an overflow detect circuit for each ADC channel; these bits are read only. 1

means an overflow has been detected in the past, and reading this register resets all OVF bits.

OVF

ADC Overflow flag

xx xxx0

ADC1 overflow input not detected

xx xxx1

ADC1 overflow input detected

xx xx0x

ADC2 overflow input not detected

xx xx1x

ADC2 overflow input detected

xx x0xx

ADC3 overflow input not detected

xx x1xx

ADC3 overflow input detected

xx 0xxx

ADC4 overflow input not detected

xx 1xx3x

ADC4 overflow input detected

x0 xxxx

ADC5 overflow input not detected

x1 xxxx

ADC5 overflow input detected

0x xxxx

ADC6 overflow input not detected

1x xxxx

ADC6 overflow input detected

Table 29. Register: ADC Control 3

DEC

HEX

ATMDAD

ATSPAD

—

OVFP

ATMDAD

ADC Attenuation mode

This bit controls the ADC attenuation mode. ATAD1[7:0] to ATAD6[7:0] are simply used for ATMDAD = 0, and

ATAD0[7:0] + ATAD1[7:0] to ATAD0[7:0] + ATAD6[7:0] in decibel number are used for ATMDAD = 1.

Default value: 0.

ATMDAD

ADC Attenuation mode

Each channel with independent data (default)

All channels with preset (independent) data + master (common) data in decibel number

ATSPAD

ADC Attenuation speed

This bit controls the ADC attenuation Speed, N × 2048/fS for ATSPAD = 0 and N × 4096/fS for ATSPAD = 1. N is

automatically selected according to the ADC sampling mode, SRAD: N = 1 for single and N = 2 for dual rate.

Default value: 0.

ATSPAD

ADC Attenuation speed

N × 2048/fS (default)

N × 4096/fS

OVFP

ADC Overflow flag polarity select

This bit controls the polarity of the overflow flag pin.

Default value: 0.

OVFP

ADC Overflow flag polarity select

High for overflow detect (default)

Low for overflow detect

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