PCM3168APAPR datasheet(35/66 Pages) TI1

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LRCKDA

(Slave)

BCKDA

Left-JustifiedMode

DIN1

(Dual)

I SMode

DIN1

(Dual)

Left-JustifiedMode

DIN1/2

(Quad)

I SMode

DIN1/2

(Quad)

1/f (256BCKsatDualRate,128BCKsatQuadRate)

23 22

1 0

23 22

1 0

23 22

1 0

23 22

Ch1

32BCKs

Ch2

32BCKs

Ch3

32BCKs

Ch4

32BCKs

Ch5

32BCKs

Ch6

32BCKs

Ch7

32BCKs

Ch8

32BCKs

Ch1/Ch5

32BCKs

Ch2/Ch6

32BCKs

Ch3/Ch7

32BCKs

Ch4/Ch8

32BCKs

PCM3168A

www.ti.com

SBAS452A – SEPTEMBER 2008 – REVISED JANUARY 2016

Figure 53. Audio Data Format: 24-Bit High-Speed TDM Format

(SCKI = 128 fS, 256 fS, DAC, and Slave Mode Only)

9.4.5 Synchronization With the Digital Audio System

The PCM3168A device operates under the system clock (SCKI) and the audio sampling rate (LRCKAD/DA).

Therefore, SCKI and LRCKAD/DA must have a specific relationship in slave mode. The PCM3168A device does

not need a specific phase relationship between the audio interface clocks (LRCKAD/DA, BCKAD/DA) and the

system clock (SCKI), but does require a specific frequency relationship (ratiometric) between LRCKAD/DA,

BCKAD/DA, and SCKI.

If the relationship between SCKI and LRCKDA changes more than ±2 BCKDA clocks because of jitter, sampling

frequency change, and so forth, the DAC internal operation halts within 1 / fS, and the analog output is forced into

VCOMDA (0.5 VCCDA1) until re-synchronization between SCKI, LRCKDA, and BCKDA is completed and then

tDACDLY3 passes. If the relationship between SCKI and LRCKAD changes more than ±2 BCKADs because of

jitter, sampling frequency change, and so forth, the ADC internal operation halts within 1 / fS, and the digital

output is forced into a 0 code until re-synchronization between SCKI, LRCKAD, and BCKAD is completed and

then tADCDLY3 passes. In the event the change is less than ±2 BCKAD/DAs, re-synchronization does not occur,

and this analog/digital output control and discontinuity do not occur.

Figure 7 shows the DAC analog output and ADC digital output for loss of synchronization. During undefined data

periods, some noise may be generated in the audio signal. Also, the transition of normal to undefined data and

undefined (or zero) data to normal data creates a discontinuity of data on the analog and digital outputs, which

then may generate some noise in the audio signal.

Both ADC outputs (DOUTx) and DAC outputs (VOUTx) hold the previous state if the system clock halts, but the

asynchronous and re-synchronization processes would occur after the system clock resumes. Figure 7 shows

DAC outputs and ADC outputs for loss of synchronization.

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