PCM3168APAPR datasheet(11/66 Pages) TI1

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PCM3168A

www.ti.com

SBAS452A – SEPTEMBER 2008 – REVISED JANUARY 2016

Electrical Characteristics (continued)

At TA = 25°C, VCCAD1 = VCCAD2 = VCCDA1 = VCCDA2 = 5 V, VDD1 = VDD2 = 3.3 V, fS = 48 kHz, SCKI = 512 fS, 24-bit

data, Sampling Mode = Auto for ADC and DAC, and Interface Mode = Slave for ADC and DAC, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DYNAMIC PERFORMANCE(9)(10)

fS = 48 kHz

–94

–88

THD+N, VOUT = 0 dB

fS = 96 kHz

–94

fS = 192 kHz

–94

fS = 48 kHz, EIAJ, A-

105

112

weighted

fS = 96 kHz, EIAJ, A-

Dynamic range

112

weighted

fS = 192 kHz, EIAJ, A-

112

weighted

fS = 48 kHz, EIAJ, A-

105

112

weighted

fS = 96 kHz, EIAJ, A-

S/N ratio

112

weighted

fS = 192 kHz, EIAJ, A-

112

weighted

fS = 48 kHz

102

108

Channel separation

fS = 96 kHz

108

(between one channel and others)

fS = 192 kHz

108

ANALOG OUTPUT

Output voltage

Differential

1.6 × VCCDA1

VPP

Center voltage

0.5 × VCCDA1

To AC-coupled GND(11)

Load impedance

Ω

To DC-coupled GND(11)

f = 20 kHz

–0.04

Lowpass filter frequency response

f = 44 kHz

–0.18

DIGITAL FILTER PERFORMANCE(12)

Slow roll-off

Passband (single, dual)

0.454 × fS

Passband (quad)

0.432 × fS

Stop band (single, dual)

0.546 × fS

Stop band (quad)

0.569 × fS

Passband ripple

≤ 0.454 × fS

±0.0018

Stop band attenuation

> 0.546 × fS, 0.569 × fS

–75

DIGITAL FILTER PERFORMANCE

Slow roll-off

Passband

0.328 × fS

Stop band

0.673 × fS

Passband ripple

< 0.328 × fS

±0.0013

Stop band attenuation

> 0.673 × fS

–75

(9)

In differential mode at VOUTx± pin, fOUT = 1 kHz, using Audio Precision System II, RMS mode with 20-kHz lowpass filter and 400-Hz

highpass filter.

(10) fS = 48 kHz : SCKI = 512 fS (single), fS = 96 kHz : SCKI = 256 fS (dual), fS = 192 kHz : SCKI = 128 fS (quad).

(11) Allowable minimum input resistance of differential to single-ended converter with D to S Gain = G is calculated as (1 + 2G)/(1 + G) × 5k

for AC-coupled and (1+ 0.9G)/(1 + G) × 15k for DC-coupled connection, refer to Figure 61 and Figure 62 of the Application Information

section.

(12) Exclude single and dual at 128 fS, 192 fS system clock and quad at 256 fS to 768 fS system clock, and specifications for quad, single,

and dual are respectively applied in reverse for them.

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