PCM3168APAPR datasheet(32/66 Pages) TI1

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PCM3168A

SBAS452A – SEPTEMBER 2008 – REVISED JANUARY 2016

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The de-emphasis filter is enabled by the MDI/SDA/DEMP pin. The de-emphasis frequency is fixed at 44.1 kHz in

hardware control mode, as shown in Table 9. The software mode provides full selections of 32 kHz, 44.1 kHz,

and 48 kHz.

Table 9. Hardware Control Mode

DEMP (DE-EMPHASIS FILTER ENABLE)

DESCRIPTION

Low

44.1 kHz, de-emphasis disabled

High

44.1 kHz, de-emphasis enabled

The audio interface and the sampling mode are selected by the MS/ADR0/MD0 and MDO/ADR1/MD1 pins. The

selectable multiple of the master mode audio interface is limited between 256 fS, 384 fS, and 512 fS; the

selectable sampling mode is limited as shown in Table 10. The software mode provides full selections.

Table 10. Selectable Sampling Mode

DESCRIPTION

MD1

MD0

INTERFACE MODE

SAMPLING MODE

ADC

DAC

ADC

DAC

Low

Slave(1)

Auto(2)

Low

High

Master, 512 fS

Slave(1)

Single rate

Auto(2)

High

Low

Master, 384 fS

Slave(1)

Dual rate

Auto(2)

High

Master, 256 fS

Slave(1)

Dual rate

Auto(2)

(1)

The multiples between system clock and sampling frequency are automatically detected; 256 fS, 384 fS, 512 fS, and 768 fS are

acceptable for ADC operation, and 128 fS, 192 fS, 256 fS, 384 fS, 512 fS, and 768 fS are acceptable for DAC operation.

(2)

The sampling mode is automatically set as single rate for 512 fS and 768 fS, dual rate for 256 fS and 384 fS, and quad rate for 128 fS and

198 fS, according to the detected multiples between the system clock and sampling clock.

9.4.3 Audio Serial Port Operation

The PCM3168A device audio serial port consists of 11 signals: BCKDA, BCKAD, LRCKDA, LRCKAD, DIN1,

DIN2, DIN3, DIN4, DOUT1, DOUT2, and DOUT3. The PCM3168A device also supports audio-interface mode,

slave mode, and master mode. The BCKAD/DA is a bit clock input at the slave mode and an output at the

master mode. The LRCKAD/DA is a left/right word clock or frame synchronization clock input at slave mode and

output at master mode. The DIN1/2/3/4 are the audio data inputs for the DAC. The DOUT1/2/3 are the audio

data outputs from the ADC. BCKAD, LRCKAD and DOUT1/2/3 are used for the ADC, and BCKDA, LRCKDA and

DIN1/2/3/4 are used for the DAC.

9.4.4 Audio Data Interface Formats and Timing

The PCM3168A device supports eight audio data interface formats for the ADC and DAC separately in both

master and slave modes: 24-bit I2S, 24-bit left-justified, 24-bit right-justified, 16-bit right-justified, 24-bit left-

justified mode DSP, 24-bit I2S mode DSP, 24-bit left-justified mode TDM, and 24-bit I2S mode TDM format. The

PCM3168A device also supports two audio data interface formats for the DAC and slave mode: 24-bit left-

justified mode high-speed TDM and 24-bit I2S mode high-speed TDM format. In the case of I2S, left-justified, and

right-justified data formats, 64 BCKs, 48 BCKs, and 32 BCKs per LRCK period are supported, but 48 BCKs are

limited in slave mode and 32 BCKs are limited in slave mode 16-bit right-justified only. In the case of TDM data

format in single rate, BCKAD/DA, LRCKAD/DA, DOUT1, and DIN1 are used. In the case of TDM data format in

dual rate, BCKAD/DA, LRCKAD/DA, DOUT1/2, and DIN1/2 are used. In the case of high-speed TDM format in

dual rate, BCKDA, LRCKDA, and DIN1 are used. In the case of high-speed TDM format in quad rate, BCKDA,

LRCKDA, and DIN1/2 are used. TDM format and high-speed TDM format are supported only at SCKI = 512 fS,

256 fS, 128 fS, and fBCK ≤ fSCKI. The audio data formats are selected by MC/SCL/FMT in hardware control mode

and registers 65 and 81 in software control mode. All data must be in binary twos complement, MSB first.

Figure 47 through Figure 53 show 10 audio interface data formats. Table 11 summarizes the applicable formats

and describes the relationships among them and the respective restrictions with mode control.

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