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PCM3168APAPR Datasheet(PDF) 13 Page - Texas Instruments

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Part # PCM3168APAPR
Description  Audio Codec
PDF  66 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

PCM3168APAPR Datasheet(HTML) 13 Page - Texas Instruments

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PCM3168A
www.ti.com
SBAS452A – SEPTEMBER 2008 – REVISED JANUARY 2016
8.7 Timing Requirements: Power-On Reset
Refer to Figure 2.
SINGLE
DUAL
QUAD
UNIT
DAC delay time internal reset release to
tDACDLY1
3600
7200
14400
Period of LRCKDA
VOUT start
tDACDLY2
DAC fade-in/fade-out time
2048
4096
8192
Period of LRCKDA
ADC delay time internal reset release to
tADCDLY1
4800
9600
N/A
Period of LRCKAD
DOUT start
tADCDLY2
ADC fade-in/fade-out time
2048
4096
N/A
Period of LRCKAD
8.8 Timing Requirements: Audio Interface for Left-Justified, Right-Justified, and I
2S (Slave
Mode)
(1)
Refer to Figure 3.
MIN
NOM
MAX
UNIT
tBCY
BCKAD/DA cycle time
75
ns
tBCH
BCKAD/DA pulse width high
35
ns
tBCL
BCKAD/DA pulse width low
35
ns
tLRS
LRCKAD/DA setup time to BCKAD/DA rising edge
10
ns
tLRH
LRCKAD/DA hold time to BCKAD/DA rising edge
10
ns
tDIS
DIN1/2/3/4 setup time to BCKDA rising edge
10
ns
tDIH
DIN1/2/3/4 hold time to BCKDA rising edge
10
ns
tDOD
DOUT1/2/3 delay time from BCKAD falling edge
0
30
ns
(1)
Load capacitance of output is 20 pF.
8.9 Timing Requirements: Audio Interface for Left-Justified, Right-Justified, and I
2S (Master
Mode)
(1)
Refer to Figure 4.
MIN
TYP
MAX
UNIT
tBCY
BCKAD/DA cycle time
1 / (64 × fS)
tBCH
BCKAD/DA pulse width high
0.4 × tBCY
0.5 × tBCY
0.6 × tBCY
tBCL
BCKAD/DA pulse width low
0.4 × tBCY
0.5 × tBCY
0.6 × tBCY
tLRD
LRCKAD/DA delay time from BCKAD/DA falling edge
–10
20
ns
tDIS
DIN1/2/3/4 setup time to BCKDA rising edge
10
ns
tDIH
DIN1/2/3/4 hold time to BCKDA rising edge
10
ns
tDOD
DOUT1/2/3 delay time from BCKAD falling edge
–10
20
ns
(1)
Load capacitance of output is 20 pF.
Copyright © 2008–2016, Texas Instruments Incorporated
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Product Folder Links: PCM3168A



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