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MB9B360R Datasheet(PDF) 141 Page - Cypress Semiconductor |
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MB9B360R Datasheet(HTML) 141 Page - Cypress Semiconductor |
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141 / 166 page  Document Number: 002-04872 Rev.*A Page 141 of 166 MB9B360R Series 12.5 12-bit A/D Converter Electrical Characteristics for the A/D Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V) Parameter Symbol Pin name Value Unit Remarks Min Typ Max Resolution - - - - 12 bit Integral Nonlinearity - - - 4.5 - + 4.5 LSB AVRH = 2.7V to 5.5V Differential Nonlinearity - - -2.5 - + 2.5 LSB Zero transition voltage VZT AN00 to AN23 - 15 - + 15 mV Full-scale transition voltage VFST AN00 to AN23 AVRH - 15 - AVRH + 15 mV Conversion time - - 0.5* 1 - - μs AVCC ≥ 4.5V Sampling time Ts - *2 - 10 μs AVCC ≥ 4.5V *2 - AVCC < 4.5V Compare clock cycle* 3 Tcck - 25 - 1000 ns AVCC ≥ 4.5V 50 - 1000 AVCC < 4.5V State transition time to operation permission Tstt - 1.0 - - μs Power supply current (analog + digital) - AVCC - 0.69 0.92 mA A/D 1unit operation - 1.0 18 μA When A/D stop Reference power supply current (between AVRH and AVSS) - AVRH - 1.1 1.97 mA A/D 1unit operation AVRH=5.5V 0.3 6.3 μA When A/D stop Analog input capacity CAIN - - - 12.05 pF Analog input resistance RAIN - - - 1.2 k Ω AVCC ≥ 4.5V 1.8 AVCC < 4.5V Interchannel disparity - - - - 4 LSB Analog port input current - AN00 to AN23 - - 5 μA Analog input voltage - AN00 to AN23 AVSS - AVRH V Reference voltage - AVRH 2.7 - AVCC V *1: The conversion time is the value of sampling time (Ts) + compare time (Tc). The condition of the minimum conversion time is when the value of sampling time: 150ns, the value of compare time: 350ns (AVCC ≥ 4.5V). Ensure that it satisfies the value of sampling time (Ts) and compare clock cycle (Tcck). For setting* 4 of sampling time and compare clock cycle, see "Chapter: A/D Converter" in "FM4 Family Peripheral Manual Analog Macro Part". The register setting of the A/D Converter is reflected by the peripheral clock timing. The sampling and compare clock are set at Base clock (HCLK). *2: A necessary sampling time changes by external impedance. Ensure that it set the sampling time to satisfy (Equation 1). *3: The compare time (Tc) is the value of (Equation 2). *4: The register setting of the A/D Converter is reflected by the timing of the APB bus clock. The sampling clock and compare clock are set in base clock (HCLK). About the APB bus number which the A/D Converter is connected to, see “Block Diagram” in this data sheet. |
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