V62SLASH12615-01XE-R datasheet(15/92 Pages) TI1

15 / 92 page

DP83848-EP

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SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

Table 2-7. Strap Options(1)(2)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

PHY ADDRESS [4:0]: The DP83848 provides five PHY address pins, the state of which are latched into the

PHYAD0 (COL)

S, O, PU

PHYCTRL register at system Hardware-Reset.

The DP83848 supports PHY Address strapping values 0 (<00000>) through 31 (<11111>). A PHY Address of 0 puts

the part into the MII Isolate Mode. The MII isolate mode must be selected by strapping Phy Address 0; changing to

PHYAD1 (RXD_0)

S, O, PD

Address 0 by register write will not put the Phy in the MII isolate mode. Please refer to section 2.3 for additional

information.

PHYAD2 (RXD_1)

PHYAD0 pin has weak internal pull-up resistor.

PHYAD3 (RXD_2)

PHYAD[4:1] pins have weak internal pull-down resistors.

PHYAD4 (RXD_3)

AN_EN

Auto-Negotiation Enable: When high, this enables Auto-Negotiation with the capability set by ANO and AN1 pins.

S, O, PU

(LED_ACT/COL)

When low, this puts the part into Forced Mode with the capability set by AN0 and AN1 pins.

AN0 / AN1: These input pins control the forced or advertised operating mode of the DP83848 according to the

AN_1

following table. The value on these pins is set by connecting the input pins to GND (0) or VCC (1) through 2.2 k

(LED_SPEED)

resistors. These pins should NEVER be connected directly to GND or VCC.

AN_0 (LED_LINK)

The value set at this input is latched into the DP83848 at Hardware-Reset.

The float/pull-down status of these pins are latched into the Basic Mode Control Register and the Auto_Negotiation

Advertisement Register during Hardware-Reset.

The default is 111 since these pins have internal pull-ups.

AN_EN

AN1

AN0

Forced Mode

10BASE-T, Half-Duplex

10BASE-T, Full-Duplex

100BASE-TX, Half-Duplex

100BASE-TX, Full-Duplex

AN_EN

AN1

AN0

Advertised Mode

10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

10BASE-T Half-Duplex

100BASE-TX, Half-Duplex

10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

MII MODE SELECT: This strapping option pair determines the operating mode of the MAC Data Interface. Default

MII_MODE

operation (No pull-ups) will enable normal MII Mode of operation. Strapping MII_MODE high will cause the device to

S, O, PD

(RX_DV)

be in RMII or SNI mode of operation, determined by the status of the SNI_MODE strap. Since the pins include

internal pull-downs, the default values are 0.

SNI_MODE

The following table details the configurations:

(TXD_3)

MII_MODE

SNI_MODE

MAC Interface Mode

MII Mode

RMII Mode

10 Mb SNI Mode

LED CONFIGURATION: This strapping option determines the mode of operation of the LED pins. Default is Mode 1.

Mode 1 and Mode 2 can be controlled via the strap option. All modes are configurable via register access.

LED_CFG (CRS)

S, O, PU

See Table 4-3 for LED Mode Selection.

MDIX ENABLE: Default is to enable MDIX. This strapping option disables Auto-MDIX. An external pull-down will

MDIX_EN (RX_ER)

S, O, PU

disable Auto- MDIX mode.

(1)

The DP83848 uses many of the functional pins as strap options. The values of these pins are sampled during reset and used to strap

the device into specific modes of operation. The functional pin name is indicated in parentheses.

(2)

A 2.2 k

Ω resistor should be used for pull-down or pull-up to change the default strap option. If the default option is required, then there is

no need for external pull-up or pull down resistors. Since these pins may have alternate functions after reset is deasserted, they should

not be connected directly to VCC or GND.

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