V62SLASH12615-01XE-R datasheet(70/92 Pages) TI1

70 / 92 page

DP83848-EP

SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

www.ti.com

Table 9-4. Basic Mode Status Register (BMSR), Address 0x01 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

Auto Negotiation Ability:

Auto-Negotiation Ability

1, RO/P

1 = Device is able to perform Auto-Negotiation

0 = Device is not able to perform Auto-Negotiation

Link Status:

1 = Valid link established (for either 10 or 100 Mb/s operation)

0 = Link not established

Link Status

0, RO/LL

The criteria for link validity is implementation specific. The occurrence of

a link failure condition will causes the Link Status bit to clear. Once

cleared, this bit may only be set by establishing a good link condition and

a read via the management interface.

Jabber Detect: This bit only has meaning in 10 Mb/s mode

1 = Jabber condition detected

0 = No Jabber

Jabber Detect

0, RO/LH

This bit is implemented with a latching function, such that the occurrence

of a jabber condition causes it to set until it is cleared by a read to this

Extended Capability:

Extended Capability

1, RO/P

1 = Extended register capabilities

0 = Basic register set capabilities only

9.2.3

PHY Identifier Register #1 (PHYIDR1)

The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83848. The Identifier

consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number

and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY

Identifier if desired. The PHY Identifier is intended to support network management. National's IEEE

assigned OUI is 080017h.

Table 9-5. PHY Identifier Register #1 (PHYIDR1), Address 0x02

BIT

BIT NAME

DEFAULT

DESCRIPTION

OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are stored

<0010 0000 0000 0000>,

15:0

OUI_MSB

in bits 15 to 0 of this register. The most significant two bits of the OUI

RO/P

are ignored (the IEEE standard refers to these as bits 1 and 2).

9.2.4

PHY Identifier Register #2 (PHYIDR2)

Table 9-6. PHY Identifier Register #2 (PHYIDR2), Address 0x03

BIT

BIT NAME

DEFAULT

DESCRIPTION

OUI Least Significant Bits:

15:10

OUI_LSB

<0101 11>, RO/P

Bits 19 to 24 of the OUI (080017h) are mapped from bits 15 to 10 of

this register respectively.

Vendor Model Number:

9:4

VNDR_MDL

<00 1001 >, RO/P

The six bits of vendor model number are mapped from bits 9 to 4

(most significant bit to bit 9).

Model Revision Number:

Four bits of the vendor model revision number are mapped from bits 3

3:0

MDL_REV

<0000>, RO/P

to 0 (most significant bit to bit 3). This field will be incremented for all

major device changes.

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