V62SLASH12615-01XE-R datasheet(55/92 Pages) TI1

55 / 92 page

DP83848-EP

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SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

6.2.11 Bad SSD Detection

A bad start of stream delimiter (Bad SSD) is any transition from consecutive idle code-groups to non-idle

code-groups which is not prefixed by the code-group pair /J/K.

If this condition is detected, the DP83848 will assert RX_ER and present RXD[3:0] = 1110 to the MII for

the cycles that correspond to received 5B code-groups until at least two IDLE code groups are detected.

In addition, the false carrier sense counter register (FCSCR) will be incremented by one.

Once at least two IDLE code groups are detected, RX_ER and CRS become de-asserted.

6.3

10BASE-T Transceiver Module

The 10BASE-T transceiver module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision,

heartbeat, loopback, jabber, and link integrity functions, as defined in the standard. An external filter is not

required on the 10BASE-T interface since this is integrated inside the DP83848. This section focuses on

the general 10BASET system level operation.

6.3.1

Operational Modes

6.3.1.1

Half Duplex Mode

In half duplex mode the DP83848 functions as a standard IEEE 802.3 10BASE-T transceiver supporting

the CSMA/CD protocol.

6.3.1.2

Full Duplex Mode

In full duplex mode the DP83848 is capable of simultaneously transmitting and receiving without asserting

the collision signal. The DP83848's 10 Mb/s ENDEC is designed to encode and decode simultaneously.

6.3.2

Smart Squelch

The smart squelch is responsible for determining when valid data is present on the differential receive

inputs. The DP83848 implements an intelligent receive squelch to ensure that impulse noise on the

receive inputs will not be mistaken for a valid signal. Smart squelch operation is independent of the

10BASE-T operational mode.

The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the

IEEE 802.3 10BSE-T standard) to determine the validity of data on the twisted pair inputs (refer to

Figure 6-5).

The signal at the start of a packet is checked by the smart squelch and any pulses not exceeding the

squelch level (either positive or negative, depending upon polarity) will be rejected. Once this first squelch

level is overcome correctly, the opposite squelch level must then be exceeded within 150 ns. Finally the

signal must again exceed the original squelch level within a 150 ns to ensure that the input waveform will

not be rejected. This checking procedure results in the loss of typically three preamble bits at the

beginning of each packet.

Only after all these conditions have been satisfied will a control signal be generated to indicate to the

remainder of the circuitry that valid data is present. At this time, the smart squelch circuitry is reset.

Valid data is considered to be present until the squelch level has not been generated for a time longer

than 150 ns, indicating the end of packet. Once good data has been detected, the squelch levels are

reduced to minimize the effect of noise causing premature end of packet detection.

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