V62SLASH12615-01XE-R datasheet(68/92 Pages) TI1

68 / 92 page

DP83848-EP

SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

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9.2

In the register definitions under the ‘Default’ heading, the following definitions hold true:

•

RW = Read Write access

•

SC = Register sets on event occurrence and Self-Clears when event ends

•

RW/SC = Read Write access/Self Clearing bit

•

RO = Read Only access

•

COR = Clear on Read

•

RO/COR = Read Only, Clear on Read

•

RO/P = Read Only, Permanently set to a default value

•

LL = Latched Low and held until read, based upon the occurrence of the corresponding event

•

LH = Latched High and held until read, based upon the occurrence of the corresponding event

9.2.1

Basic Mode Control Register (BMCR)

Table 9-3. Basic Mode Control Register (BMCR), Address 0x00

BIT

BIT NAME

DEFAULT

DESCRIPTION

Reset:

1 = Initiate software Reset/Reset in Process

Reset

0, RW/SC

0 = Normal operation

This bit, which is self-clearing, returns a value of one until the reset

process is complete. The configuration is re-strapped.

Loopback:

1 = Loopback enabled

0 = Normal operation

The loopback function enables MII transmit data to be routed to the MII

Loopback

0, RW

receive data path.

Setting this bit may cause the descrambler to lose synchronization and

produce a 500

μs “dead time” before any valid data will appear at the MII

receive outputs.

Speed Select:

When auto-negotiation is disabled writing to this bit allows the port speed

to be selected.

Speed Selection

Strap, RW

1 = 100 Mb/s

0 = 10 Mb/s

Auto-Negotiation Enable:

Strap controls initial value at reset

1 = Auto-Negotiation Enabled - bits 8 and 13 of this register are ignored

Auto-Negotiation Enable

Strap, RW

when this bit is set.

0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed

and duplex mode.

Power Down:

1 = Power down

0 = Normal opeation.

Power Down

0, RW

Setting this bit powers down the PHY. Only the register block is enabled

during a power down condition. This bit is OR’d with the input from the

PWR_DOWN/INT pin. When the active low PWR_DOWN/INT pin is

asserted, this bit will be set.

Isolate:

1 = Isolates the Port from the MII with the exception of the serial man-

Isolate

0, RW

agement.

0 = Normal operation

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