V62SLASH12615-01XE-R datasheet(12/92 Pages) TI1

12 / 92 page

DP83848-EP

SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

www.ti.com

2.4

Terminal Descriptions

All DP83848 signal pins are I/O cells regardless of the particular use. The definitions below define the

functionality of the I/O cells for each pin.

Type: I - Input

Type: O - Output

Type: I/O - Input/Output

Type OD - Open Drain

Type: PD, PU - Internal Pulldown/Pullup

Type: S - Strapping Pin (All strap pins have weak internal pull-ups or pull-downs. If the default strap value

is needed to be changed then an external 2.2 k

Ω resistor should be used.)

Table 2-1. Serial Management Interface

TERMINAL

I/O

DESCRIPTION

NAME

NO.

MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface

MDC

which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum

clock rate.

MANAGEMENT DATA I/O: Bi-directional management instruction/ data signal that may be sourced by the station

MDIO

I/O

management entity or the PHY. This pin requires a 1.5 k

Ω pullup resistor.

Table 2-2. MAC Data Interface

TERMINAL

I/O

DESCRIPTION

NAME

NO.

MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode or 2.5 MHz in 10 Mb/s mode derived

from the 25 MHz reference clock.

Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit

TX_CLK

and receive.

SNI TRANSMIT CLOCK: 10 MHz Transmit clock output in 10 Mb SNI mode. The MAC should source TX_EN

and TXD_0 using this clock.

MII TRANSMIT ENABLE: Active high input indicates the presence of valid data inputs on TXD[3:0].

TX_EN

I, PD

RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0].

SNI TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD_0.

MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous to the TX_CLK

TXD_0

(2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode).

RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous to the 50 MHz

TXD_1

reference clock.

TXD_2

SNI TRANSMIT DATA: Transmit data SNI input pin, TXD_0, that accept data synchronous to the TX_CLK

(10 MHz in 10 Mb/s SNI mode).

TXD_3

S, I, PD

MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100 Mb/s mode and 2.5 MHz for

10 Mb/s mode.

RX_CLK

Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit

and receive.

SNI RECEIVE CLOCK: Provides the 10 MHz recovered receive clocks for 10 Mb/s SNI mode.

MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the corresponding RXD[3:0].

MII mode by default with internal pulldown.

RX_DV

S, O, PD

RMII Synchronous Receive Data Valid: This signal provides the RMII Receive Data Valid indication

independent of Carrier Sense.

This pin is not used in SNI mode.

OVERVIEW

Submit Documentation Feedback

Product Folder Links: DP83848-EP

V62/12615-01XE-R Datasheet(PDF) 12 Page - Texas Instruments

V62/12615-01XE-R Datasheet(HTML) 12 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Datasheet Download

Link URL