V62SLASH12615-01XE-R datasheet(77/92 Pages) TI1

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DP83848-EP

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SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

9.3.3

MII Interrupt Status and Miscellaneous Control Register (MISR)

This register contains event status and enables for the interrupt function. If an event has occurred since

the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the

set to allow interrupts. The status indications in this register will be set even if the interrupt is not enabled.

Table 9-14. MII Interrupt Status and Miscellaneous Control Register (MISR), Address 0x12

BIT

BIT NAME

DEFAULT

DESCRIPTION

RESERVED

0, RO

RESERVED: Writes ignored, Read as 0

Energy Detect interrupt:

1 = Energy detect interrupt is pending and is cleared by the current

ED_INT

0, RO/COR

read

0 = No energy detect interrupt pending

Change of Link Status interrupt:

1 = Change of link status interrupt is pending and is cleared by the

LINK_INT

0, RO/COR

current read

0 = No change of link status interrupt pending

Change of speed status interrupt:

1 = Speed status change interrupt is pending and is cleared by the

SPD_INT

0, RO/COR

current read

0 = No speed status change interrupt pending

Change of duplex status interrupt:

1 = Duplex status change interrupt is pending and is cleared by the

DUP_INT

0, RO/COR

current read

0 = No duplex status change interrupt pending

Auto-Negotiation Complete interrupt:

1 = Auto-negotiation complete interrupt is pending and is cleared by

ANC_INT

0, RO/COR

the current read

0 = No Auto-negotiation complete interrupt pending

False Carrier Counter half-full interrupt:

1 = False carrier counter half-full interrupt is pending and is cleared by

FHF_INT

0, RO/COR

the current read

0 = No false carrier counter half-full interrupt pending

Receive Error Counter half-full interrupt:

1 = Receive error counter half-full interrupt is pending and is cleared

RHF_INT

0, RO/COR

by the current read

0 = No receive error carrier counter half-full interrupt pending

RESERVED

0, RO

RESERVED: Writes ignored, Read as 0

ED_INT_EN

0, RW

Enable Interrupt on energy detect event

LINK_INT_EN

0, RW

Enable Interrupt on change of link status

SPD_INT_EN

0, RW

Enable Interrupt on change of speed status

DUP_INT_EN

0, RW

Enable Interrupt on change of duplex status

ANC_INT_EN

0, RW

Enable Interrupt on Auto-negotiation complete event

FHF_INT_EN

0, RW

Enable Interrupt on False Carrier Counter Register half-full event

RHF_INT_EN

0, RW

Enable Interrupt on Receive Error Counter Register half-full event

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