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V62/12615-01XE-R Datasheet(PDF) 47 Page - Texas Instruments

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Part # V62/12615-01XE-R
Description  PHYTER MILITARY TEMPERATURE SINGLE PORT 10/100 MB/S ETHERNET PHYSICAL LAYER TRANSCEIVER
PDF  92 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

V62/12615-01XE-R Datasheet(HTML) 47 Page - Texas Instruments

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MDC
MDIO
(STA)
Idle
Start
Opcode
(Write)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h = BMCR)
TA
Register Data
Idle
z
z
0
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
z
z
MDC
MDIO
(STA)
Idle
Start
Opcode
(Read)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h = BMCR)
TA
Register Data
z
MDIO
(PHY)
z
z
Idle
z
z
z
z
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
DP83848-EP
www.ti.com
SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013
Table 5-2. Typical MDIO Frame Format
MII MANAGEMENT SERIAL
<idle><start><op code><device addr><reg addr><turnaround><data><idle>
PROTOCOL
Read Operation
<idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
Write Operation
<idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
Figure 5-1. Typical MDC/MDIO Read Operation
Figure 5-2. Typical MDC/MDIO Write Operation
5.4.3
Serial Management Preamble Suppression
The DP83848 supports a preamble suppression mode as indicated by a one in bit 6 of the basic mode
status register (BMSR, address 01h.) If the station management entity (i.e. MAC or other management
controller) determines that all PHYs in the system support preamble suppression by returning a one in this
bit, then the station management entity need not generate preamble for each management transaction.
The DP83848 requires a single initialization sequence of 32 bits of preamble following hardware/software
reset.
This requirement is generally met by the mandatory pull-up resistor on MDIO in conjunction with a
continuous MDC, or the management access made to determine whether preamble suppression is
supported.
While the DP83848 requires an initial preamble sequence of 32 bits for management initialization, it does
not require a full 32-bit sequence between each subsequent transaction. A minimum of one idle bit
between management transactions is required as specified in the IEEE 802.3u specification.
Copyright © 2012–2013, Texas Instruments Incorporated
FUNCTIONAL DESCRIPTION
47
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Product Folder Links: DP83848-EP



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