V62SLASH12615-01XE-R datasheet(17/92 Pages) TI1

17 / 92 page

DP83848-EP

www.ti.com

SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

ELECTRICAL SPECIFICATIONS

3.1

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT

VCC

Supply voltage

-0.5 to 4.2

VIN

DC input voltage

-0.5 to VCC + 0.5

VOUT

DC output voltage

-0.5 to VCC + 0.5

TSTG

Storage temperature

-65 to 150

°C

Operating junction temperature

-55 to 150

°C

Lead temperature (soldering, 10 seconds)

260

°C

ESD rating (RZAP = 1.5 kΩ, CZAP = 100 pF)

3.2

Recommended Operating Conditions

(1)

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

VCC

Supply voltage

3.6

Operating free-air temperature(2)

-55

125

°C

Power dissipation

267

(1)

Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply

that the device should be operated at these limits.

(2)

Provided that Thermal Pad is soldered down.

3.3

Thermal Information

DP83848

THERMAL METRIC

PHP

UNITS

48 PINS

θJA

Junction-to-ambient thermal resistance(1)

35.74

θJCtop

Junction-to-case (top) thermal resistance(2)

21.8

θJB

Junction-to-board thermal resistance(3)

19.5

°C/W

ψJT

Junction-to-top characterization parameter(4)

1.2

ψJB

Junction-to-board characterization parameter(5)

19.4

θJCbot

Junction-to-case (bottom) thermal resistance(6)

3.2

(1)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(2)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(4)

The junction-to-top characterization parameter,

ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining

θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(5)

The junction-to-board characterization parameter,

ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining

θJA , using a procedure described in JESD51-2a (sections 6 and 7).

(6)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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ELECTRICAL SPECIFICATIONS

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