V62SLASH12615-01XE-R datasheet(79/92 Pages) TI1

79 / 92 page

DP83848-EP

www.ti.com

SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

Table 9-17. 100 Mb/s PCS Configuration and Status Register (PCSR), Address 0x16 (continued)

BIT

BIT NAME

DEFAULT

DESCRIPTION

Descrambler Timeout:

Increase the descrambler timeout. When set this should allow the

device to receive larger packets (>9k bytes) without loss of

DESC_TIME

0, RW

synchronization.

1 = 2 ms

0 = 722 µs (per ANSI X3.263: 1995 (TP-PMD) 7.2.3.3e)

RESERVED

RESERVED: Must be zero

Force 100Mb/s Good Link:

FORCE_100_OK

0, RW

1 = Forces 100Mb/s Good Link

0 = Normal 100Mb/s operation

RESERVED

RESERVED: Must be zero

RESERVED

RESERVED: Must be zero

NRZI Bypass Enable:

NRZI_BYPASS

0, RW

1 = NRZI Bypass Enabled

0 = NRZI Bypass Disabled

RESERVED

RESERVED: Must be zero

RESERVED

RESERVED: Must be zero

9.3.7

RMII and Bypass Register (RBR)

This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is

bypassed.

Table 9-18. RMII and Bypass Register (RBR), Addresses 0x17

BIT

BIT NAME

DEFAULT

DESCRIPTION

15:6

RESERVED

0, RO

Reserved: Writes ignored, Read as 0

Reduced MII Mode:

RMII_MODE

Strap, RW

0 = Standard MII Mode

1 = Reduced MII Mode

Reduce MII Revision 1.0:

0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to

RMII_REV1_0

0, RW

indicate deassertion of CRS.

1 = (RMII revision 1.0) CRS_DV will remain asserted until final data is

transferred. CRS_DV will not toggle at the end of a packet.

RX FIFO Over Flow Status:

RX_OVF_STS

0, RO

0 = Normal

1 = Overflow detected

RX FIFO Under Flow Status:

RX_UNF_STS

0, RO

0 = Normal

1 = Underflow detected

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