V62SLASH12615-01XE-R datasheet(25/92 Pages) TI1

25 / 92 page

(T/R)

IDLE

DATA

PMD input pair

CRS

T2.10.1

(J/K)

IDLE

DATA

PMD input pair

CRS

RXD[3:0]

RX_DV

RX_ER

T2.9.1

T2.9.2

DP83848-EP

www.ti.com

SLLSEC6D – SEPTEMBER 2012 – REVISED JUNE 2013

3.5.9

100BASE-TX Receive Packet Latency Timing

Figure 3-10. 100BASE-TX Receive Packet Latency Timing

xxx

PARAMETER

DESCRIPTION(1)

NOTES(2) (3)

MIN

TYP

MAX

UNIT

T2.9.1

Carrier Sense ON Delay

100 Mb/s Normal mode

bits

T2.9.2

Receive Data Latency

100 Mb/s Normal mode

bits

(1)

Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.

(2)

1 bit time = 10 ns in 100 Mb/s mode.

(3)

PMD Input Pair voltage amplitude is greater than the Signal Detect Turn-On Threshold Value.

3.5.10 100BASE-TX Receive Packet Deassertion Timing

Figure 3-11. 100BASE-TX Receive Packet Deassertion Timing

xxx

PARAMETER

DESCRIPTION

NOTES(1) (2)

MIN

TYP

MAX

UNIT

T2.10.1

Carrier Sense OFF Delay

100 Mb/s Normal mode

bits

(1)

Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.

(2)

1 bit time = 10 ns in 100 Mb/s mode

ELECTRICAL SPECIFICATIONS

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