PM6344 datasheet(32/256 Pages) PMC

32 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

Pin Name

Type

Pin No.

Function

BRCLK

Input

Backplane Receive Clock (BRCLK). When the multiplex

enable (MENB) input is deasserted high, BRCLK is a

2.048MHz clock with optional gapping for adaptation to

non-uniform backplane data streams. BRCLK is

common to all four framers. The EQUAD may be

configured to ignore the BRCLK input and use the

RCLKO[x] signal in its place when the ELST is

bypassed or the RCLKOSEL register bit is set.

MRCLK

Multiplex Receive Clock (MRCLK). When the multiplex

enable (MENB) input is asserted low, MRCLK is a

16.384 MHz clock. MRFPI is sampled on the rising

edge of MRCLK and MRD is updated on the rising edge

of MRCLK. The multiplexed bus can not be used if the

ELST is bypassed or the RCLKOSEL register bit is set.

BRFPI

Input

Backplane Frame Pulse Input (BRFPI). When the

multiplex enable (MENB) input is deasserted high, this

input is used to frame align the received data to the

system backplane. BRFPI is common to all four

framers. If frame alignment only is required, a pulse at

least 1 BRCLK cycle wide must be provided on each

BRFPI every 256 bit periods.

MRFPI

Multiplexed Frame Pulse Input (MRFPI). When the

multiplex enable (MENB) input is asserted low, this input

aligns all four sets of PCM and signaling streams to

allow bit interleaved multiplexing. If frame alignment

only is required, a pulse no more than 1 MRCLK cycle

wide must be provided on each MRFPI every 2048 bit

periods.

PM6344 Datasheet(PDF) 32 Page - PMC-Sierra, Inc

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