PM6344 datasheet(82/256 Pages) PMC

82 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

dual-rail inputs, which bypass the TRAN and input directly into the jitter

attenuator. It is expected that the framing bits be already inserted into the

dual-rail streams before they are input on BTDP[x] and BTDN[x]. When

BTX2RAIL is set to logic 0, the multifunction pins become the BTPCM[x] and

BTSIG[x] digital inputs.

BTXMFP:

The BTXMFP bit selects the type of backplane frame alignment signal

presented to the transmitter BTFP[x] input. When BTXMFP is set to logic 1,

BTFP[x] must be brought high to mark bit 1 of frame 1 of every 16 frame

signaling multiframe and brought low following bit 1 of frame 1 of every 16

frame CRC multiframe. This mode allows both multiframe alignments to be

independently controlled using the single BTFP[x] signal. Note that if the

signaling and CRC multiframe alignments are coincident, BTFP[x] must pulse

high for 1 BTCLK[x] cycle at a multiple of 16 frames. When BTXMFP is set to

logic 0, a rising edge on the BTFP[x] indicates the first bit in each frame.

When the multiplexed transmit backplane is selected (MENB is low), the

BTXMFP bit must be set to the same value in all four quadrants of the

EQUAD. The MTFP pin is used in a similar way as BTFP[x] but is only

sampled on the clock cycles corresponding to the first multiplexed PCM

stream (destined for transmitter number one). MTFP must be brought high to

mark bit 1 of frame 1 of the first multiplexed PCM stream (destined for

transmitter number one) of every 16 frame signaling multiframe and brought

low following bit 1 of frame 1 of the first multiplexed PCM stream of every 16

frame CRC multiframe. All four interfaces will have the same frame alignment.

Upon reset of the EQUAD, these bits are cleared to zero.

PM6344 Datasheet(PDF) 82 Page - PMC-Sierra, Inc