PM6344 datasheet(37/256 Pages) PMC

37 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

Pin Name

Type

Pin No.

Function

TDN[1]

TDN[2]

TDN[3]

TDN[4] /

Output

Transmit Digital Negative Line Pulse (TDN[4:1] ). These

signals are available on the output when the EQUAD is

configured to transmit dual-rail data. The TDN[x] signal

can be formatted for either RZ or NRZ waveforms, and

can be enabled to be updated on the rising or falling

edge of the associated TCLKO[x].

TFLG[1]

TFLG[2]

TFLG[3]

TFLG[4]

Transmit FIFO Flag (TFLG[4:1] ). These signals are

available when configured to transmit single-rail data.

The TFLG[x] output indicates when the transmit rate

conversion FIFO in DJAT is nearing an empty or a full

condition. Either indication may be selected. This

output may be enabled to be updated on the rising or

falling edge of the associated TCLKO[x].

TCLKI[1]

TCLKI[2]

TCLKI[3]

TCLKI[4]

Input

Transmit Clock Input (TCLKI[x]). This input signal is

used to generate the TCLKO[x] clock signal. Depending

upon the configuration of the EQUAD, TCLKO[x] may be

derived directly from TCLKI[x] by dividing TCLKI[x] by 8,

or TCLKO[x] may be derived from TCLKI[x] after jitter

attenuation. If TCLKI[x] is jitter-free when divided down

to 8 kHz, then it is possible to derive TCLKO[x] from

TCLKI[x] when TCLKI[x] is a multiple of 8 kHz (i.e. Nx8

kHz, for N equals 1 to 256). The EQUAD may be

configured to ignore the TCLKI[x] input and utilize

BTCLK[x] or RCLKO[x] instead. RCLKO[x] is also

substituted for TCLKI[x] if line loopback is enabled.

XCLK/

Input

Crystal Clock Input (XCLK). This signal provides timing

for many portions of the EQUAD. Depending on the

configuration of the EQUAD, XCLK is nominally a

49.152 MHz or 16.384 MHz 50% duty cycle clock.

When transmit clock generation or jitter attenuation is

not required, XCLK may be driven with a 16.384 MHz

clock. When transmit clock generation or jitter

attenuation is required, XCLK must be driven with a

49.152 MHz clock.

VCLK

Vector Clock (VCLK). The VCLK signal is used during

EQUAD production test to verify internal functionality.

INTB

Output

Active low open-drain Interrupt signal (INTB). This

signal goes low when an unmasked interrupt event is

detected on any of the internal interrupt sources,

including the internal HDLC transceiver. Note that INTB

will remain low until all active, unmasked interrupt

sources are acknowledged at their source.

PM6344 Datasheet(PDF) 37 Page - PMC-Sierra, Inc

PM6344 Datasheet(HTML) 37 Page - PMC-Sierra, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL