PM6344 datasheet(93/256 Pages) PMC

93 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

Bit

Type

Function

Default

Bit 7

Unused

Bit 6

Unused

Bit 5

R/W

PAYLB

Bit 4

R/W

LINELB

Bit 3

Unused

Bit 2

R/W

DDLB

Bit 1

Unused

Bit 0

R/W

TXDIS

This register allows software to enable diagnostic modes.

PAYLB:

The PAYLB bit selects the payload loopback mode, where the received data

output from the ELST is internally connected to the transmit data input of the

TRAN. The data read out of ELST is timed to the transmitter clock, and the

transmit frame alignment is used to synchronize the output frame alignment

of ELST. During payload loopback, the data output on BRPCM[x] is forced to

logic 1. When PAYLB is set to logic 1, the payload loopback mode is enabled.

When PAYLB is set to logic 0, the loopback mode is disabled.

LINELB:

The LINELB bit selects the line loopback mode, where the recovered positive

and negative pulse outputs from the CDRC block are internally connected to

the digital inputs of the DJAT. When LINELB is set to logic 1, the line

loopback mode is enabled. When LINELB is set to logic 0, the line loopback

mode is disabled. Note that when line loopback is enabled, the Timing

Options Register settings should be reviewed to ensure the options are such

that data will pass error-free and "jitter"-free through DJAT (typically, the

default setting, 00H, for register 7 will be appropriate for line loopback).

DDLB:

The DDLB bit selects the diagnostic digital loopback mode, where the

transmit side outputs from DJAT are internally connected to the receive side

inputs. When DDLB is set to logic 1, the diagnostic digital loopback mode is

PM6344 Datasheet(PDF) 93 Page - PMC-Sierra, Inc

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