PM6344 datasheet(75/256 Pages) PMC

75 / 256 page

STANDARD PRODUCT

PMC-Sierra, Inc.

PM6344 EQUAD

PMC-951013

ISSUE 5

QUADRUPLE E1 FRAMER

RDLEOME:

The RDLEOME bit enables the RFDL end-of-message interrupt to also

generate an interrupt on the microprocessor interrupt, INTB. This allows a

single microprocessor to service the RFDL without needing to interface to the

DMA control signals. When RDLEOME is set to logic 1, an end-of-message

event causing an EOM interrupt in the RFDL (which is visible on the

RDLEOM output pin when RXDMASIG is logic 1) also causes an interrupt to

be generated on the INTB output. When RDLEOME is set to logic 0, an EOM

interrupt event in the RFDL does not cause an interrupt on INTB. NOTE:

within the RFDL, an end-of-message event causes an interrupt on both the

EOM and INT RFDL interrupt outputs. See the Operation section for further

details on using the RFDL.

TDLINTE:

The TDLINTE bit enables the XFDL request for service interrupt to also

generate an interrupt on the microprocessor interrupt, INTB. This allows a

single microprocessor to service the XFDL without needing to interface to the

DMA control signals. When TDLINTE is set to logic 1, an request for service

interrupt event in the XFDL (which is visible on the TDLINT output pin when

TXDMASIG is logic 1) also causes and interrupt to be generated on the INTB

output. When TDLINTE is set to logic 0, an interrupt event in the XFDL does

not cause an interrupt on INTB.

TDLUDRE:

The TDLUDRE bit enables the XFDL transmit data underrun interrupt to also

generate an interrupt on the microprocessor interrupt, INTB. This allows a

single microprocessor to service the XFDL without needing to interface to the

DMA control signals. When TDLUDRE is set to logic 1, an underrun event

causing an interrupt in the XFDL (which is visible on the TDLUDR output pin

when TXDMASIG is logic 1) also causes and interrupt to be generated on the

INTB output. When TDLUDRE is set to logic 0, an underrun event in the

XFDL does not cause an interrupt on INTB.

Upon reset of the EQUAD, these bits are cleared to zero.

PM6344 Datasheet(PDF) 75 Page - PMC-Sierra, Inc