PM8313 datasheet(47/192 Pages) PMC

47 / 192 page

PM8313 D3MX

DATA SHEET

PMC-920702

ISSUE 5

M13 MULTIPLEXER

Whenever counter data is transferred into the holding registers, an interrupt is

generated, providing the interrupt is enabled. If the holding registers have not

been read since the last interrupt, an overrun status bit is set.

8.3

Path Maintenance Data Link Receiver

The RFDL Data Link Receiver is a microprocessor peripheral used to receive

LAPD/HDLC frames from the DS3 C-bit parity path maintenance data link

The RFDL detects the change from flag characters to the first byte of data,

removes stuffed zeros on the incoming data stream, receives frame data, and

calculates the CRC-CCITT frame check sequence (FCS).

Received data is placed into a 4-level FIFO buffer. The Status Register contains

bits which indicate overrun, end of message, flag detected, and buffered data

available.

On end of message, the Status Register also indicates the FCS status and the

number of valid bits in the final data byte. Interrupts are generated when one,

two or three (programmable count) bytes are stored in the FIFO buffer. Interrupts

are also generated when the terminating flag sequence, abort sequence, or

FIFO buffer overrun are detected.

8.4

Alarm And Control Channel Bit Oriented Code Detector

The Bit-Oriented Code Detector (RBOC) Block detects the presence of 63 of the

64 possible bit-oriented codes (BOCs) transmitted in the DS3 C-bit parity far-end

alarm and control (FEAC) channel. The 64th code ("111111") is similar to the

HDLC flag sequence and is ignored.

Bit-oriented codes are received on the FEAC channel as 16-bit sequences each

consisting of 8 ones, a zero, 6 code bits, and a trailing zero

("111111110xxxxxx0"). BOCs are validated when repeated at least 10 times .

The RBOC can be enabled to declare a received code valid if it has been

observed for 8 out of 10 times or for 4 out of 5 times, as specified by the AVC bit

in the RBOC Configuration/Interrupt Enable Register.

Valid BOCs are indicated through the RBOC Interrupt Status Register. The BOC

bits are set to all ones ("111111") if no valid code has been detected. The RBOC

can be programmed to generate an interrupt when a detected code has been

validated and when the code disappears.

PM8313 Datasheet(PDF) 47 Page - PMC-Sierra, Inc