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PM8313 Datasheet(PDF) 78 Page - PMC-Sierra, Inc |
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PM8313 Datasheet(HTML) 78 Page - PMC-Sierra, Inc |
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78 / 192 page ![]() PM8313 D3MX DATA SHEET PMC-920702 ISSUE 5 M13 MULTIPLEXER 68 Register 08H: Master Interrupt Source #1 Bit Type Function Default Bit 7 R REG2 0 Bit 6 R REG3 0 Bit 5 R XFDLINT 0 Bit 4 R MX23 0 Bit 3 R DS3FRMR 0 Bit 2 R RFDLINT 0 Bit 1 R RFDLEOM 0 Bit 0 R RBOC 0 This register allows software to determine which of the MX23, DS3 FRMR, or RBOC TSBs produced the interrupt on the INTB output pin and whether there are any pending interrupts in the other two Interrupt Source registers. Also, this register reports whether the RFDL or XFDL TSBs have generated interrupts on their respective HDLC Controller outputs (i.e. RDLINT, RDLEOM, TDLINT, TDLUDR). These four signals can be configured for active-low, open-drain output and wire-ORed together with the INTB output to generate a global microprocessor interrupt. Reading this register does not remove the interrupt indication; the corresponding TSB's interrupt status register must be read to remove the interrupt indication. RBOC: If the RBOC bit is a logic 1, the FEAC RBOC TSB is generating an interrupt. Register 33H should be read to determine which event in RBOC has caused to interrupt. RFDLEOM: If the RFDLEOM bit is a logic 1, the RFDL TSB is generating an interrupt due to an end of message occurrence (also visible on the RDLEOM output when configured for internal HDLC, i.e. REXHDLC=0). RFDLINT: If the RFDLINT bit is a logic 1, the RFDL TSB is generating an interrupt (also visible on the RDLINT output when configured for internal HDLC, i.e. REXHDLC=0). |
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