HMC832LP6GETR datasheet(30/49 Pages) AD

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Data Sheet

HMC832

Rev. A | Page 29 of 48

POWER-DOWN MODE

Note that the VCO subsystem is not affected by the CEN or soft

reset. Therefore, device power-down is a two step process.

Power down the VCO by writing 0 to VCO Register 1 via

Power-down the PLL by pulling the CEN pin (Pin 17) low

(assuming there are no SPI overrides (Register 0x01[0] = 1)).

Pulling the CEN pin low disables all analog functions and

internal clocks. Current consumption typically drops below

10 μA in the power-down state. The serial port still

responds to normal communication in power-down mode.

It is possible to ignore the CEN pin by setting Register 0x01[0]

= 0. Control of the power-down mode then comes from the

serial port register, Register 0x01[1].

It is also possible to leave various blocks turned on when in

power-down (see Register 0x01), as listed in Table 10.

Table 10. Bit and Block Assignments for Register 0x01

Bit Assignment

Block Assignment

Bit 2

Internal bias reference sources

Bit 3

PD block

Bit 4

CP block

Bit 5

Reference path buffer

Bit 6

VCO path buffer

Bit 7

Digital I/O test pads

To mute the output but leave the PLL and VCO locked, see the

VCO Output Mute Function section.

GENERAL-PURPOSE OUTPUT (GPO) PIN

The PLL shares the LD_SDO (lock detect/serial data output)

pin to perform various functions. Although the pin is most

commonly used to read back registers from the chip via the SPI,

it is also capable of exporting a variety of signals and real-time

test waveforms (including lock detect). It is driven by a tristate

CMOS driver with ~200 Ω ROUT. It has logic associated with it

to dynamically select whether the driver is enabled, and to

decide which data to export from the chip.

In its default configuration, after power-on reset, the output

driver is disabled, and only drives during appropriately

addressed SPI reads. This allows it to share the output with

other devices on the same bus.

The pin driver is enabled if the chip is addressed; that is, the last

three bits of SPI cycle = 000b before the rising edge of SEN. If

SEN rises before SCK has clocked in an invalid (non zero) chip

address, the HMC832 starts to drive the bus.

To monitor any of the GPO signals, including lock detect, set

stops the LDO driver from tristating and means that the SDO

line cannot be shared with other devices.

The HMC832 naturally switches away from the GPO data and

exports the SDO during an SPI read. To prevent this automatic

data selection, and always select the GPO signal, set Bit 6 of

noise performance at this output is poor and uncharacterized.

Also, the GPO output should not be toggling during normal

operation because it may degrade the spectral performance.

Note that there are additional controls available, which may be

helpful when sharing the bus with other devices.



To disable the driver completely, set Register 0x08[5] = 0 (it

takes precedence over all else).



To disable either the pull-up or pull-down sections of the

driver, Register 0x0F[8] = 1 or Register 0x0F[9] = 1,

respectively.

Example scenarios are listed in Table 11. The signals that are

available on the GPO are selected by changing the GPO Select

Table 11. Driver Scenarios

Scenario

Action

Drive SDO During Reads, Tristate

Otherwise (Allow Bus Sharing)

None required

Drive SDO During Reads, Lock

Detect Otherwise

Set GPO Select Register 0x0F[4:0]

= 00001b (default)

Set Register 0x0F[7] = 1, prevent

GPO driver disable

Always Drive Lock Detect

Set Register 0x0F[6] = 1, prevent

automux of SDO

Set the GPO Select

(default)

Set Register 0x0F[7] = 1, prevent

GPO driver disable

CHIP IDENTIFICATION

PLL subsystem version information may be read by reading the

content of read only register, chip_ID in Register 0x00. It is not

possible to read the VCO subsystem version.

SERIAL PORT

The SPI protocol has the following general features:



3-bit chip address, can address up to eight devices

connected to the serial bus.



Wide compatibility with multiple protocols from multiple

vendors.



Simultaneous write/read during the SPI cycle.



5-bit address space.



3-wire for write only capability, 4-wire for read/write

capability.

Typical serial port operation can be run with SCLK at speeds up

to 50 MHz.

Serial Port Initialization at Power-Up

At power-up, it is required that both SEN and SCK lines are

initially held low, and that the first rising edge occurs on the

SCK line before any rising edges occur on the SEN line.

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