HMC832LP6GETR datasheet(25/49 Pages) AD

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HMC832

Data Sheet

Table 9. Typical Digital Lock Detect Window

LD Timer Speed

Bits[11:10]

Digital Lock Detect Window Size Nominal Value (ns)

Fastest 00

6.5

100

195

8.9

12.8

130

255

7.1

9.2

13.3

138

272

Slowest 11

7.6

10.2

15.4

172

338

LD Timer Divide

Setting

Bits[9:7]

000

001

010

011

100

101

110

111

Digital Window Configuration Example

Assuming, fractional mode, with a 50 MHz PD and a

•

Charge pump gain of 2 mA (Register 0x09[13:7] = 0x64,

•

Up offset (Register 0x09[22:21] = 01b)

•

Offset current magnitude of +400 μA (Register 0x09[20:14]

= 0x50)

Applying Equation 10, the required LD window size is:

LD Window (sec) =

)

(

(sec)

)

(

)

(

)

(













−

Locating the Table 9 value that is closest to this result is, in this

case, 13.3 ≈ 13.33. To set the digital LD window size, program

according to Table 9.

There is always a good solution for the lock detect window for a

given operating point. The user should understand, however,

that one solution does not fit all operating points. As observed

from Equation 10 and Equation 11, if the charge pump offset or

PD frequency is changed significantly, then the lock detect

window may need to be adjusted.

Configuring the LD_SDO Pin for LD Output

Setting Register 0x0F[7] = 1 and Register 0x0F[4:0] = 1 displays

the lock detect flag on the LD_SDO pin of the HMC832. When

locked, LD_SDO is high. As the name suggests, LD_SDO pin is

multiplexed between the LD and the serial data output (SDO)

signals. Therefore, LD is available on the LD_SDO pin at all

times except when a serial port read is requested, in which case

the pin reverts temporarily to the serial data output pin, and

returns to the lock detect flag after the read is completed.

LD can be made available on LD_SDO pin at all times by

writing Register 0x0F[6] = 1. In that case, the HMC832 does

not provide any readback functionality because the SDO signal

is not available.

Cycle Slip Prevention (CSP)

When changing VCO frequency and the VCO is not yet locked

to the reference, the instantaneous frequencies of the two PD

inputs are different, and the phase difference of the two inputs

at the PD varies rapidly over a range much greater than ±2π

radians. Because the gain of the PD varies linearly with phase

up to ±2π, the gain of a conventional PD cycles from high gain,

when the phase difference approaches a multiple of 2π, to low

gain, when the phase difference is slightly larger than a multiple

of 0 radians. The output current from the charge pump cycles

from maximum to minimum, even though the VCO has not yet

reached its final frequency.

The charge on the loop filter small capacitor may actually

discharge slightly during the low gain portion of the cycle. This

can make the VCO frequency reverse temporarily during

locking. This phenomenon is known as cycle slipping. Cycle

slipping causes the pull-in rate during the locking phase to vary

cyclically. Cycle slipping increases the time to lock to a value

greater than that predicted by normal small signal Laplace

transform analysis.

The HMC832 PD features an ability to reduce cycle slipping

during acquisition. The cycle slip prevention (CSP) feature

increases the PD gain during large phase errors. The specific

phase error that triggers the momentary increase in PD gain is

set via Register 0x0B[8:7].

Frequency Tuning

The HMC832 VCO subsystem always operates in fundamental

frequency of operation (1500 MHz to 3000 MHz). The HMC832

generates frequencies below its fundamental frequency (25 MHz to

1500 MHz) by tuning to the appropriate fundamental frequency

and selecting the appropriate output divider setting (divide by

2/4/6/ … 60/62) in VCO_REG 0x02[5:0].

The HMC832 automatically controls frequency tuning in the

fundamental band of operation, for more information see the

VCO Autocalibration section.

To tune to frequencies below the fundamental frequency range

(<1500 MHz) it is required to tune the HMC832 to the appropriate

fundamental frequency, then select the appropriate output divider

setting (divide by 2/4/6/ … 60/62) in VCO_REG 0x02[5:0].

Integer Mode

The HMC832 is capable of operating in integer mode. For

integer mode, set the following registers:

•

Disable the fractional modulator, Register 0x06[11] = 0

•

Bypass the modulator circuit, Register 0x06[7] = 1

In integer mode, the VCO step size is fixed to that of the PD

frequency. Integer mode typically has a 3 dB lower phase noise

than fractional mode for a given PD operating frequency.

Integer mode, however, often requires a lower PD frequency to

meet step size requirements. The fractional mode advantage is

that higher PD frequencies can be used; therefore, lower phase

noise can often be realized in fractional mode. Disable charge

pump offset when in integer mode.

Rev. A | Page 24 of 48

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