HMC832LP6GETR datasheet(23/49 Pages) AD

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HMC832

Data Sheet

Charge Pump Phase Offset

In integer mode, the phase detector operates with zero offset.

The divided reference signal and the divided VCO signal arrive

at the phase detector inputs at the same time. Integer mode

does not require any CP offset current. When operating in

integer mode, disable CP offset in both directions (up and

down) by writing Register 0x09[22:21] = 00b, and set the CP

offset magnitude to zero by writing Register 0x09[20:14] = 0.

In fractional mode, CP linearity is of paramount importance.

Any nonlinearity degrades phase noise and spurious perfor-

mance. These nonlinearities are eliminated by operating the PD

with an average phase offset, either positive or negative (either

the reference or the VCO edge always arrives first at the PD,

that is, leads).

A programmable CP offset current source is used to add dc

current to the loop filter and to create the desired phase offset.

Positive current causes the VCO to lead, negative current causes

the reference to lead.

The CP offset is controlled via Register 0x09. The phase offset is

scaled from 0° to 360°, where they arrive a full cycle late.

The specific level of charge pump offset current (Register 0x09,

Bits[20:14]) is provided in Equation 9 and plotted in Figure 44.

Required CP Offset =

min [(4.3 × 10−9 × fPD × ICP), 0.25 × ICP]

(9)

where:

fPD is the comparison frequency of the phase detector (Hz).

ICP is the full-scale current setting (A) of the switching charge

pump (set in Register 0x09[6:0] and Register 0x09[13:7]).

Figure 44. Recommended CP Offset Current vs. PD Frequency for Typical CP

Gain Currents, Calculated Using Equation 9

Do not allow the required CP offset current to exceed 25% of

the programmed CP current. It is recommended to enable the

up offset and disable the down offset by writing Register 0x09,

Bits[22:21] = 01b.

Operation with CP offset influences the required configuration

of the lock detect function. See the description of the lock

detect function in the Lock Detect section.

Phase Detector Functions

to control special phase detector features.

Setting Register 0x0B[5] = 0 masks the PD up output, which

prevents the charge pump from pumping up.

Setting Register 0x0B[6] = 0, masks the PD down output, which

prevents the charge pump from pumping down.

Clearing both Register 0x0B[5] and Register 0x0B[6] tristates

the charge pump while leaving all other functions operating

internally.

PD force up (Register 0x0B[9] = 1) and PD force down

(Register 0x0B[10] = 1) allows the charge pump to be forced up

or down, respectively. This forces the VCO to the ends of the

tuning range, which is useful in testing the VCO.

Reference Input Stage

Figure 45. Reference Path Input Stage

The reference buffer provides the path from an external

reference source (generally crystal-based) to the R divider, and

eventually to the phase detector. The buffer has two modes of

operation controlled by Register 0x08[21]. High gain (Regis-

ter 0x08[21] = 0) is recommended below 200 MHz, and high

frequency (Register 0x08[21] = 1) for 200 MHz to 350 MHz

operation. The buffer is internally dc biased with 100 Ω internal

termination. For a 50 Ω match, add an external 100 Ω resistor

to ground followed by an ac coupling capacitor (impedance less

than 1 Ω).

At low frequencies, a relatively square reference is recommended to

maintain a high input slew rate. At higher frequencies, use a

square or sinusoid.

Table 8 shows the recommended operating regions for different

reference frequencies. If operating outside these regions, the

device usually still operates, but with degraded reference path

phase noise performance.

When operating at 50 MHz, the input referred phase noise of

the PLL is between −148 dBc/Hz and −150 dBc/Hz at a 10 kHz

offset, depending upon the mode of operation. To avoid degra-

dation of the PLL noise contribution, the input reference signal

should be 10 dB better than this floor. Note that such low levels

are only necessary if the PLL is the dominant noise contributor

and these levels are required for the system goals.

100

200

300

400

500

600

700

100

PHASE DETECTOR FREQUENCY (MHz)

CP CURRENT = 2.5mA

CP CURRENT = 2mA

CP CURRENT = 1mA

XREFP

80Ω

20Ω

AC COUPLE

100Ω

RVDD

Rev. A | Page 22 of 48

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