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HMC832LP6GETR Datasheet(PDF) 16 Page - Analog Devices |
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HMC832LP6GETR Datasheet(HTML) 16 Page - Analog Devices |
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16 / 49 page ![]() Data Sheet HMC832 Rev. A | Page 15 of 48 HMC832 SPI. As a result, writes to the PLL Register Map are written directly and immediately, whereas the writes to the VCO Subsystem Register Map are written to the PLL subsystem Register 0x05 and forwarded via the internal VCO SPI (VSPI) to the VCO subsystem. This is a form of indirect addressing. Note that VCO subsystem registers are write only and cannot be read. More information is available in the VCO Serial Port Interface (VSPI) section. VCO Serial Port Interface (VSPI) The HMC832 communicates with the internal VCO subsystem via an internal 16-bit VCO SPI. The internal serial port controls the step tuned VCO and other VCO subsystem functions. Note that the internal VCO subsystem SPI (VSPI) runs at the rate of the autocalibration FSM clock, tFSM, (see the VCO Autocalibration section) where the FSM clock frequency cannot be greater than 50 MHz. The VSPI clock rate is set by Register 0x0A[14:13]. Writes to the control registers of the VCO are handled indirectly via writes to Register 0x05 of the HMC832. A write to HMC832 Register 0x05 causes the internal PLL subsystem to forward the packet, MSB first, across its internal serial link to the VCO subsystem, where it is interpreted. VSPI Use of Register 0x05 The packet data written into Register 0x05 is subparsed by logic at the VCO subsystem into the following three fields: Field 1—Bits[2:0]: 3-bit VCO_ID, target subsystem address = 000b. Field 2—Bits[6:3]: 4-bit VCO_REGADDR, the internal register address inside the VCO subsystem. Field 3—Bits[15:7]: 9-bit VCO_DATA, data field to write to the VCO register. For example, to write 0_1111_1110 into Register 2 of the VCO subsystem (VCO_ID = 000b), and set the VCO output divider to divide by 62, the following needs to be written to Register 0x05 = 0_1111_1110b, 0010b, 000b or equivalently, Register 0x05 = 7F10. During autocalibration, the autocalibration controller writes into the VCO register address specified by the VCO_ID and VCO_REGADDR, as stored in Register 0x05[2:0] and Register 0x05[6:3], respectively. Autocalibration requires that these values be zero (Register 0x05[6:0] = 0); otherwise, when they are not zero (Register 0x05[6:0] ≠ 0), autocalibration does not function. To ensure that the autocalibration functions, it is critical to write Register 0x05[6:0] = 0 after the last VCO subsystem write prior to an output frequency change triggered by a write to either Register 0x03 or Register 0x04. However, it is impossible to write only Register 0x05[6:0] = 0 (VCO_REGADDR) without writing Register 0x05[15:7] (VCO_DATA). Therefore, to ensure that the VCO_DATA (Register 0x05[15:7]) in VCO_REGADDR 0x00 is not changed, it is required to read the switch settings provided in Regis- ter 0x10[7:0], and then rewrite them to Register 0x05[15:7], as shown in the following example: 1. Read Register 0x10 2. Write to Register 0x05 the following: a. Register 0x05[15:14] = Register 0x10[7:6] b. Register 0x05[13] = 1, reserved bit c. Register 0x05[12:8] = Register 0x10[4:0] d. Register 0x05[7:0] = 0 Changing the VCO subsystem configuration (VCO Subsystem Register Map section) without following this procedure results in a failure to lock to the desired frequency. For applications not using the read functionality of the HMC832 SPI, in which Register 0x10 cannot be read, it is possible to write Register 0x05 = 0x0 to set Register 0x05[6:0] = 0, which also sets the VCO subband setting equal to zero (Register 0x05[15:7] = 0), effectively programming incorrect VCO subband settings and causing the HMC832 to lose lock. This procedure is then immediately followed by a write to: Register 0x03, if in integer mode. Register 0x04, if in fractional mode. This write effectively retriggers the autocalibration state machine, forcing the HMC832 to relock whether in integer or fractional mode. This procedure causes the HMC832 to lose lock and relock after every VCO subsystem change. Typical output frequency and lock time is shown in Figure 27 and Figure 30, and is typically in the order of 100 μs for a phase settling of 10°, and is also dependent on loop filter design (loop filter bandwidth and loop filter phase margin). |
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