HMC832LP6GETR datasheet(41/49 Pages) AD

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HMC832

Data Sheet

Rev. A | Page 40 of 48

Bit

Type

Name

Width

Default

Description

14:13

R/W

FSM/VSPI clock select

These bits set the autocalibration FSM and VSPI clock (50 MHz

maximum)

0: input crystal reference

1: input crystal reference divide by 4

2: input crystal reference divide by 16

3: input crystal reference divide by 32

16:15

R/W

Reserved

PHASE DETECTOR (PD) REGISTER

Table 25. Register 0x0B, PD Register (Default 0x0F8061)

Bit

Type

Name

Width

Default

Description

2:0

R/W

PD_DEL_SEL

Sets PD reset path delay (recommended setting is 001).

4:3

R/W

Reserved

Reserved.

R/W

PD_UP_EN

Enables the PD up output.

R/W

PD_DN_EN

Enables the PD down output.

8:7

R/W

CSP mode

Cycle slip prevention mode. This delay varies by ±10% with temperature, and

±12% with process. Extra current is driven into the loop filter when the phase error

is larger than the following:

0 = disabled

1 = 5.4 ns

2 = 14.4 ns

3 = 24.1 ns

R/W

Force CP up

Forces CP up output to turn on; use for test only.

R/W

Force CP DN

Forces CP down output to turn on; use for test only.

23:11

R/W

Reserved

496d

0x1F0

Reserved.

EXACT FREQUENCY MODE REGISTER

Table 26. Register 0x0C, Exact Frequency Mode Register (Default 0x000000)

Bit

Type

Name

Width

Default

Description

13:0

R/W

Number of

Channels per fPD

The comparison frequency divided by the correction rate must be an integer.

Frequencies at exactly the correction rate have zero frequency error.

0: disabled.

1: disabled.

2:16383d (0x3FFF).

HMC832LP6GETR Datasheet(PDF) 41 Page - Analog Devices

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