HMC832LP6GETR datasheet(32/49 Pages) AD

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Data Sheet

HMC832

Serial Port Read Operation

In general, the LD_SDO line is always active during the

write cycle. During any SPI cycle, LD_SDO contains the

data from the current address written in Register 0x0[4:0].

If Register 0x0[4:0] is not changed, the same data is always

present on LD_SDO during a SPI cycle.

If a read is required from a specific address, it is necessary to

write the required address to Register 0x0[4:0] in the first SPI

cycle, then in the next SPI cycle, the desired data becomes

available on LD_SDO. A typical read cycle is shown in Figure 48.

An example of the two cycle procedure to read from any

random address is as follows:

1. The master (host), on the first 24 falling edges of SCLK

places 24-bit data, D23:D0, MSB first, on SDI as shown in

Figure 48. Set D23:D5 to zero. D4:D0 = address of the

2. The slave (HMC832) shifts in data on SDI on the first 24

rising edges of SCK.

3. The master places the 5-bit register address , R4:R0, (the

read address register), MSB first, on the next five falling

edges of SCK (25th to 29th falling edges). R4:R0 = 00000.

4. The slave shifts the register bits on the next five rising

edges of SCK (25th to 29th rising edges).

5. The master places the 3-bit chip address, A2:A0, MSB first,

on the next three falling edges of SCK (30th to 32nd falling

edges). The chip address is always 000b.

6. The slave shifts the chip address bits on the next three

rising edges of SCK (30th to 32nd rising edges).

7. The master asserts SEN after the 32nd rising edge of SCK.

8. The slave registers the SDI data on the rising edge of SEN.

9. The master clears SEN to complete the the address transfer

of the two part read cycle.

10. If a write data to the chip is not needed at the same time as

the second cycle occurs, then it is recommended to simply

rewrite the same contents on SDI to Register 0x00 on the

readback portion of the cycle.

11. The master places the same SDI data as the previous cycle

on the next 32 falling edges of SCK.

12. The slave (HMC832) shifts the SDI data on the next 32

rising edges of SCK.

13. The slave places the desired read data (that is, data from

the address specified in Register 0x00[4:0] of the first

cycle) on LD_SDO, which automatically switches to SDO

mode from LD mode, disabling the LD output.

14. The master asserts SEN after the 32nd rising edge of SCK to

complete the cycle and revert back to lock detect on

LD_SDO.

Rev. A | Page 31 of 48

HMC832LP6GETR Datasheet(PDF) 32 Page - Analog Devices

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