ST25R3910 datasheet(9/65 Pages) STMICROELECTRONICS

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ST25R3910

Functional overview

1.1.7

Power supply regulators

Integrated power supply regulators ensure a high power supply rejection ratio for the

complete reader system. If the reader system PSRR has to be improved, the command

Adjust Regulators is sent. As a result of this command, the power supply level of VDD is

measured in maximum load conditions and the regulated voltage reference is set 250 mV

below this measured level to assure a stable regulated supply. The resulting regulated

voltage is stored in a register. It is also possible to define regulated voltage by writing a

configuration register. To decouple any noise sources from different parts of the IC there are

three regulators integrated with separated external blocking capacitors (the regulated

voltage of all of them is the same). One regulator is for the analog blocks,the other is for the

antenna drivers. Logic and digital I/O pads are supplied directly from VDD (negative supply

pin for logic and digital I/O is separated to avoid coupling of logic induced noise in the

substrate).

This block additionally generates a reference voltage for the analog processing

(AGD - analog ground). This voltage also has an associated external buffer capacitor.

1.1.8

POR and Bias

This block provides the bias current and the reference voltages to all other blocks. It also

incorporates a Power on Reset (POR) circuit that provides a reset at power-up and at low

supply voltage levels.

1.1.9

ISO-14443 and NFCIP-1 framing

This block performs framing for receive and transmit according to the selected ISO mode

and bit rate settings.

In reception it takes the demodulated sub-carrier signal from the receiver. It recognizes the

SOF, EOF and data bits, performs parity and CRC check, organizes the received data in

bytes and places them in the FIFO.

During transmit, it operates inversely, it takes bytes from the FIFO, generates parity and

CRC bits, adds SOF and EOF and performs final encoding before passing the modulation

signal to the transmitter.

In Transparent mode, the framing and FIFO are bypassed, the digitized sub-carrier signal

(the receiver output), is directly sent to the SDATAO pin, and the signal applied to the

SDATAI pin is directly used to modulate the transmitter.

1.1.10

FIFO

The ST25R3910 contains a 32-byte FIFO. Depending on the mode, it contains either data

that has been received or data to be transmitted.

1.1.11

Control logic

The control logic contains I/O registers that define operation of device.

1.1.12

SPI

A 4-wire Serial Peripheral Interface (SPI) is used for communication between the external

microcontroller and the ST25R3910.

ST25R3910 Datasheet(PDF) 9 Page - STMicroelectronics

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