ST25R3910 datasheet(18/65 Pages) STMICROELECTRONICS

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Functional overview

ST25R3910

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DocID029768 Rev 2

Figure 4. Exchange of signals with microcontroller

When signal SEN is low, the SPI interface is in reset and SDATAO is in tristate; when it is

high, SPI interface is enabled. It is recommended to keep signal SEN low whenever the SPI

interface is not in use. SDATAI is sampled at the falling edge of SCLK. All communication is

done in blocks of 8 bits (bytes). The first two bits of the first byte transmitted after low to high

transition of SEN define the SPI operation mode. Table 2 defines the possible modes.

Writing data to addressable registers (Write mode)

Figure 5 and Figure 6 show cases of writing a single byte and writing multiple bytes with

auto-incrementing address. SDATAI is sampled at the falling edge of SCLK. A SEN low

pulse indicates the end of the Write command after register has been written. Auto

incrementing address is supported, this means that if after the address and first data byte

some additional data bytes are sent, they are written to addresses incremented by 1. If the

command is terminated by putting SEN low before a packet of 8 bits composing one byte is

sent, writing of this register is not performed. In case the register on the defined address

does not exist or it is a read only register, no write is performed.

Table 2. SPI operation patterns

Mode

Mode pattern (communication bits)

Mode related data

Mode

M1 M0

Write

WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0

Read

RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

FIFO load

WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0

FIFO read

RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0

Command

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ST25R3910 Datasheet(PDF) 18 Page - STMicroelectronics