ST25R3910 datasheet(16/65 Pages) STMICROELECTRONICS

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Functional overview

ST25R3910

16/65

DocID029768 Rev 2

1.2.7

Quartz crystal oscillator

The quartz crystal oscillator can operate with 13.56 and 27.12 MHz crystals. The oscillator is

based on an inverter stage supplied by controlled current source. A feedback loop is

controlling the bias current in order to regulate amplitude on XTI pin to 1 Vpp. This feedback

ensures reliable operation even in case of low quality crystals, with Rs up to 50 Ω. To enable

a fast reader start-up an interrupt is sent when the oscillator amplitude exceeds 750 mVpp.

The oscillator block always provides 13.56 MHz clock signal to the rest of the IC. In case of

27.12 MHz crystal clock signal is internally divided by two. Divider is controlled by

Configuration Register 2 bit osc. Division by two ensures that the 13.56 MHz signal has a

duty cycle of 50%, which is better for the Transmitter performance (no PW distortion). Use of

27.12 MHz crystal is therefore recommended.

In case of 13.56 MHz crystal, the bias current of stage which is digitizing oscillator signal is

increased to minimize the PW distortion. The oscillator output is also used to drive a clock

signal output pin, which can be used by the external microcontroller (MCU_CLK). By setting

Configuration Register 2 the frequency can be chosen between 13.56, 6.78 and 3.39 MHz.

Any microcontroller processing generates noise, which may be captured by the ST25R3910

receiver. Using MCU_CLK as the microcontroller clock source generates noise synchronous

with the reader carrier frequency that is filtered out by the receiver, while using some other

incoherent clock source produces noise which may generate some sideband signals

captured by Receiver. It is then recommended to use MCU_CLK as microcontroller clock

source.

1.2.8

Power supply, Regulators

The ST25R3910 includes two regulators that can be adjusted automatically to improve the

reader PSRR. VDD is an external power supply pin, used to supply the logic and digital pins.

One regulator is used to supply analog blocks (VSP_A), another is reserved for the

transmitter (VSP_RF) in order to decouple transmitter current spikes from the rest of the IC.

All negative power supply pins are externally connected to the same negative supply, the

reason for separation is the need to decouple noise induced by voltage drops on the internal

power supply lines. These pins are VSS (die substrate potential), VSN_D (negative supply

of logic and digital pads), VSN_A (negative supply of analog blocks) and VSN_RF (negative

supply of transmitter).

An additional regulator block provides AGD voltage (1.5 V), which is used as reference

potential for analog processing (analog ground). Blocking capacitors have to be connected

externally to regulator outputs and AGD pins. For pins VSP_A and VSP_RF recommended

blocking capacitors are 2.2 μF in parallel with 10 nF, for pin AGD 1 μF in parallel with 10 nF

is suggested.

The regulated voltage ranges from 2.4 to 3.4 V, with 100 mV step. Both regulators are set to

the same voltage. VSP_A regulator maximum capability is 20 mA while maximum capability

of VSP_RF regulator is 300 mA. VSP_RF regulator also has a built-in protection limiting

current to 300 mA in normal operation and to 500 mA in case of a short. The regulators are

operating when either the Operation Control Register bit en is set or pin EN is high.

In Power-down mode the regulators are not operating, VSP_A and VSP_RF are connected to

VDD through 1 kΩ resistors, to ensure smooth power-up of the system and a smooth

transitions from Stand-by mode to other operating modes. In case regulators were

regulating or were transparent at power-up a large current would be pulled from VDD supply

to charge blocking capacitors of regulated outputs, a problematic situation for battery

powered systems.

ST25R3910 Datasheet(PDF) 16 Page - STMicroelectronics

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