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CS43130 Datasheet(PDF) 67 Page - Cirrus Logic |
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CS43130 Datasheet(HTML) 67 Page - Cirrus Logic |
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67 / 137 page  DS1073F1 67 CS43130 5.10 Example Sequences 7 Start XTAL Power Down Control. 0x20000 0xF6 PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved 1 1 1 1 0 1 1 0 Power up XTAL driver 8 Apply DSD power-up initialization in Ex. 5-8 9 Configure PLL. Input is 22.5792 MHz. Output is 24.576 MHz. 10 Power up PLL Power Down Control. 0x20000 0xF2 PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT Reserved 1 1 1 1 0 0 1 0 Power up PLL 11 Set PLL Pre-Divide PLL Setting 9. 0x40002 0x03 PLL_REF_PREDIV Reserved 11 00 0000 Divide PLL Reference by 8 12 Set PLL Output Divide PLL Setting 6. 0x30008 0x08 PLL_OUT_DIV 0x08 Divide PLL output by 8 13 Set Fractional portion of PLL divide ratio PLL Setting 2. 0x30002 0x00 PLL_DIV_FRAC_0 0x00 PLL Setting 3. 0x30003 0xF7 PLL_DIV_FRAC_1 0xF7 PLL Setting 4. 0x30004 0x06 PLL_DIV_FRAC_2 0x06 14 Set integer portion of PLL divide ratio PLL Setting 5. 0x30005 0x44 PLL_DIV_INT 0x44 15 Set PLL Mode PLL Setting 8. 0x3001B 0x01 Reserved PLL_MODE Reserved 0000 00 0 1 Use 500/512 factor 16 Set PLL Calibration Ratio PLL Setting 7. 0x3000A 0x8B PLL_CAL_RATIO 0x8B Set PLL Cal Ratio to 139 17 Read Interrupt Status 1 register (0xF0000) to clear any pending interrupts. 18 Enable PLL Interrupts Interrupt Mask 1. 0xF0010 0xE1 DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK 1 1 1 0 0 0 0 1 Enable PLL Ready and Error Interrupts 19 Start PLL PLL Setting 1. 0x30001 0x01 Reserved PLL_START 000 0001 0 Start PLL 20 Configure DSDIF to playback 64•Fs DSD stream. DSDIF is configured as a slave. 21 Configure DSD Volume DSD Volume A. 0x70001 0x00 DSD_VOLUME_A 0x00 Channel A volume set to 0dB 22 Configure DSD path Signal Control1 DSD Processor Path Signal Control 1. 0x70002 0xEC Reserved DSD_VOL_BEQA DSD_SZC Reserved DSD_AMUTE DSD_AMUTE_BEQA DSD_MUTE_A DSD_MUTE_B 1 1 1 0 1 1 0 0 DSD Volume B equals DSD volume A Soft ramp control enabled Mute occurs after 256 repeated 8-bit DSD mute patterns Mute happens only when mute pattern is detected in both channels Function is disabled Function is disabled Example 5-12. Startup to DSD Playback (Cont.) STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION |
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