CS43130 datasheet(37/137 Pages) CIRRUS

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DS1073F1

CS43130

4.6 Clocking Architecture

Figure 4-13. System Clocking—External MCLK Mode

If XTAL is used, the supported crystal characteristics and frequencies are listed in Table 3-14. Based on the crystal

selection, XTAL_IBIAS must be set properly before powering up. The XTAL_IBIAS information can be found in

Section 5.3. PDN_XTAL is cleared to start the crystal oscillator. PDN_XTAL is set to power down the crystal oscillator. The

XTAL_READY_INT and XTAL_ERROR_INT status bits indicate the status of crystal operation after power-up. At tXTAL_pup

after the crystal oscillator is powered up, if the crystal is started successfully and ready to be used, XTAL_READY_INT is

set; if the crystal is started unsuccessfully, XTAL_ERROR_INT is set. The two bits are mutually exclusive when set. Both

status bits have corresponding interrupt status bits and interrupt mask bits. To be informed on the crystal status at tXTAL_

pup after power-up, unmask both interrupts before powering up the crystal.

When the MCLK is supplied to the device through the XTI/MCLK pin, it must comply with the phase-noise mask shown in

Fig. 4-14. Its frequency must be one of the nominal MCLK_INT frequencies (22.5792 or 24.576 MHz), and its duty cycle

must be between 45% to 55%.

Figure 4-14. MCLK Phase Noise Mask Without PLL

External MCLK

System

Clock

XTI/MCLK

XTO

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