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CS43130 Datasheet(PDF) 70 Page - Cirrus Logic |
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CS43130 Datasheet(HTML) 70 Page - Cirrus Logic |
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70 / 137 page  70 DS1073F1 CS43130 5.10 Example Sequences 19 Set ASP numerator ASP Numerator 1. 0x40010 0x03 ASP_N_LSB 0x03 LSB of ASP sample rate fractional divide numerator ASP Numerator 2. 0x40011 0x00 ASP_N_MSB 0x00 MSB of ASP sample rate fractional divide numerator 20 Set ASP denominator ASP Denominator 1. 0x40012 0x08 ASP_M_LSB 0x08 LSB of ASP sample rate fractional divide denominator ASP Denominator 2. 0x40013 0x00 ASP_M_MSB 0x00 MSB of ASP sample rate fractional divide denominator 21 Set ASP LRCK high time ASP LRCK High Time 1. 0x40014 0x17 ASP_LCHI_LSB 0x17 LSB of ASP LRCK high time duration ASP LRCK High Time 2. 0x40015 0x00 ASP_LCHI_MSB 0x00 MSB of ASP LRCK high time duration 22 Set ASP LRCK period ASP LRCK Period 1. 0x40016 0x2F ASP_LCPR_LSB 0x2F LSB of ASP LRCK period ASP LRCK Period 2. 0x40017 0x00 ASP_LCPR_MSB 0x00 MSB of ASP LRCK period 23 Configure ASP clock ASP Clock Configuration. 0x40018 0x1C Reserved ASP_M/SB ASP_SCPOL_OUT ASP_SCPOL_IN ASP_LCPOL_OUT ASP_LCPOL_IN 000 1 1 1 0 0 Set ASP port to be Master Set output SCLK polarity Input SCLK polarity is don't care Set Output LRCK polarity Input LRCK polarity is don't care 24 Configure ASP frame ASP Frame Configuration. 0x40019 0x0A Reserved ASP_STP ASP_5050 ASP_FSD 000 0 1 010 Configure ASP port to accept I2S input 25 Set ASP channel location ASP Channel 1 Location. 0x50000 0x00 ASP_RX_CH1 0x00 ASP Channel 1 starts on SCLK0 ASP Channel 2 Location. 0x50001 0x00 ASP_RX_CH2 0x00 ASP Channel 2 starts on SCLK0 26 Set ASP channel size and enable ASP Channel 1 Size and Enable. 0x5000A 0x06 Reserved ASP_RX_CH1_AP ASP_RX_CH1_EN ASP_RX_CH1_RES 0000 0 1 10 ASP Channel 1 active phase ASP Channel 1 enable ASP Channel 1 size is 24 bits ASP Channel 2 Size and Enable. 0x5000B 0x0E Reserved ASP_RX_CH2_AP ASP_RX_CH2_EN ASP_RX_CH2_RES 0000 1 1 10 ASP Channel 2 active phase ASP Channel 2 enable ASP Channel 2 size is 24 bits 27 Wait for interrupt. Check if PLL_READY_INT = 1 in Interrupt Status 1 register(0xF0000). 28 Configure DSD processor 29 Configure DSD volume DSD Volume A. 0x70001 0x00 DSD_VOLUME_A 0x00 Channel A volume set to 0 dB 30 Configure DSD Path Signal Control 1 DSD Processor Path Signal Control 1. 0x70002 0xEC Reserved DSD_VOL_BEQA DSD_SZC Reserved DSD_AMUTE DSD_AMUTE_BEQA DSD_MUTE_A DSD_MUTE_B 1 1 1 0 1 1 0 0 DSD Volume B equals DSD volume A Soft ramp control enabled Mute occurs after 256 repeated 8-bit DSD mute patterns Mute happens only when mute pattern is detected in both channels Function is disabled Function is disabled Example 5-13. DoP Playback with PLL (Cont.) STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION |
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