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CS43130 Datasheet(PDF) 74 Page - Cirrus Logic |
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CS43130 Datasheet(HTML) 74 Page - Cirrus Logic |
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74 / 137 page  74 DS1073F1 CS43130 5.10 Example Sequences 22 Configure PCM Path Signal Control PCM Path Signal Control 1. 0x90003 0xEC PCM_RAMP_DOWN PCM_VOL_BEQA PCM_SZC PCM_AMUTE PCM_AMUTEBEQA PCM_MUTE_A PCM_MUTE_B 1 1 10 1 1 0 0 Soft ramp down of volume on filter change Volume setting on both channels controlled by PCM_ VOLUME_A Enable soft ramp Mute after reception of 8192 samples of 0 or –1. Mute only when AMUTE condition is detected on both channels Function is disabled Function is disabled PCM Path Signal Control 2. 0x90004 0x00 Reserved PCM_INV_A PCM_INV_B PCM_SWAP_CHAN PCM_COPY_CHAN 0000 0 0 0 0 Disable all functions in this register 23 Configure HP interface 24 Configure Class H Amplifier Class H Control. 0xB0000 0x1E Reserved ADPT_PWR HV_EN EXT_VCPFILT 000 1 11 1 0 Output signal determines voltage level High voltage mode enabled Using Internal VCPFILT source. 25 Headphone Detect HP Detect. 0xD0000 0xC4 HPDETECT_CTRL HPDETECT_INV HPDETECT_RISE_DBC_TIME HPDETECT_FALL_DBC_TIME Reserved 11 0 0 0 10 0 HP Detect enabled HP detect input is not inverted Tip Sense rising debounce time set to 0 ms Tip sense falling debounce time set to 500 ms 26 Enable interrupts 27 Read Interrupt Status 1 register (0xF0000) and Interrupt Status 2 register (0xF0001) to clear sticky bits. 28 Enable headphone detect interrupts Interrupt Mask 1. 0xF0010 data(0xF0010) AND 0x9F DAC_OVFL_INT_MASK HPDETECT_PLUG_INT_MASK HPDETECT_UNPLUG_INT_MASK XTAL_READY_INT_MASK XTAL_ERROR_INT_MASK PLL_READY_INT_MASK PLL_ERROR_INT_MASK PDN_DONE_INT_MASK x 0 0 x x x x x Enable HPDETECT_PLUG interrupt Enable HPDETECT_UNPLUG interrupt 29 Enable ASP interrupts Interrupt Mask 2. 0xF0011 0x07 ASP_OVFL_INT_MASK ASP_ERROR_INT_MASK ASP_LATE_INT_MASK ASP_EARLY_INT_MASK ASP_NOLRCK_INT_MASK Reserved 0 0 0 0 0 111 Enable ASP_OVFL interrupt Enable ASP_ERROR interrupt Enable ASP_LATE interrupt Enable ASP_EARLY interrupt Enable ASP_NOLRCK interrupt 30 Initiate a soft ramp down of HPINx input to mute. 31 Disable HPINx Refer to Section 5.6.2 32 Wait for interrupt. Check if XTAL_READY_INT = 1 in Interrupt Status 1 register(0xF0000). 33 Switch MCLK source to XTAL System Clocking Control 1. 0x10006 0x04 Reserved MCLK_INT MCLK_SRC_SEL 0000 0 1 00 MCLK Source set to XTAL. MCLK_INT frequency set to 22.5792MHz 34 Wait at least 150 µs. 35 Power up HP Refer to Ex. 5-9 for PCM power-up sequence. Skip Step 1 of Ex. 5-9 (completed in Step 6 above). Example 5-15. Switching from Analog-In to PCM Playback (Cont.) STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION |
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