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CS43130 Datasheet(PDF) 45 Page - Cirrus Logic |
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CS43130 Datasheet(HTML) 45 Page - Cirrus Logic |
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45 / 137 page  DS1073F1 45 CS43130 4.9 Audio Serial Port (ASP) As shown in Fig. 4-23, if Serial Port 50/50 Mode is enabled (xSP_5050 = 1), the LRCK high duration must be programmed to the LRCK period divided by two (rounded down to the nearest integer when the LRCK period is odd). When the serial port is in 50/50 Mode, setting the LRCK high duration to a value other than half of the period results in erroneous operation. Figure 4-23. xSP_LRCK Period, High Width, 50/50 Mode SCLK LRCK Falling Edge Rising Edge xSP_LCPR xSP_LCHI SCLK LRCK Falling Edge Rising Edge xSP_LCPR xSP_LCHI Even xSP _LCPR Odd xSP _LCPR xSP_LCPR count clock is absent xSP_LCHI ... ... ... ... ... ... ... ... ... ... ... ... |
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