T48C893 datasheet(38/82 Pages) ATMEL

38 / 82 page

T48C893

Rev. A4, 22-Jan-02

38 (82)

Timer 2 output mode 7: PWM mode: Pulse–width modulation output on Timer 2 output pin (T2O)

In this mode the timer overflow defines the period and the compare register defines the duty cycle. During one period

only the first compare match occurence is used to toggle the timer output flip-flop, until the overflow all further

compare match are ignored. This avoids the situation that changing the compare register causes the occurence of sev-

eral compare match during one period. The resolution at the pulse-width modulation Timer 2 mode 1 is 12-bit and all

other Timer 2 modes are 8-bit.

255

100

255 0

150

255 0 50

255 0

100

T2R

Input clock

Counter 2/2

OVF2

CM2

INT4

T2O

load the next

compare value

T2CO2=150

load

13788

Figure 42. PWM modulation

Timer 2 Registers

Timer 2 has 6 control registers to configure the timer mode, the time interval, the input clock and its output function.

All registers are indirectly addressed using extended addressing as described in section ”Addressing peripherals”. The

alternate functions of the Ports BP41 or BP42 must be selected with the Port 4 control register P4CR, if one of the

Timer 2 modes require an input at T2I/BP41 or an output at T2O/BP42.

Timer 2 Control Register (T2C)

Address: ’7’hex – Subaddress: ’0’hex

Bit 3

Bit 2

Bit 1

Bit 0

T2C

T2CS1

T2CS0

T2TS

T2R

Reset value: 0000b

T2CS1

Timer 2 Clock Select bit 1

T2CS1

T2CS0

Input Clock (CL 2/1) of

Counter Stage 2/1

T2CS0

Timer 2 Clock Select bit 0

System clock (SYSCL)

Output signal of Timer 1 (T1OUT)

Internal shift clock of SSI (SCL)

Output signal of Timer 3 (TOG3)

T2TS

Timer 2 Toggle with Start

T2TS = 0, the output flip-flop of Timer 2 is not toggled with the timer start

T2TS = 1, the output flip-flop of Timer 2 is toggled when the timer is started with T2R

T2R

Timer 2 Run

T2R = 0, Timer 2 stop and reset

T2R = 1, Timer 2 run

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