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T48C893 Datasheet(PDF) 61 Page - ATMEL Corporation |
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T48C893 Datasheet(HTML) 61 Page - ATMEL Corporation |
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61 / 82 page ![]() T48C893 T48C893 Rev. A4, 22-Jan-02 61 (82) Serial Interface Status and Control Register (SISC) Primary register address: ’A’hex Bit 3 Bit 2 Bit 1 Bit 0 SISC write MCL RACK SIM IFN Reset value: 1111b SISC read – – – TACK ACT SRDY Reset value: xxxxb MCL Multi-Chip Link activation MCL = 1, multi-chip link disabled. This bit has to be set to ’0’ during transactions to/from the internal EEPROM MCL = 0, connnects SC and SD additional to the internal multi-chip link pads RACK Receive ACKnowledge status/control bit for I2C mode RACK = 0, transmit acknowledge in next receive telegram RACK = 1, transmit no acknowledge in last receive telegram TACK Transmit ACKnowledge status/control bit for I2C mode TACK = 0, acknowledge received in last transmit telegram TACK = 1, no acknowledge received in last transmit telegram SIM Serial Interrupt Mask SIM = 1, disable interrupts SIM = 0, enable serial interrupt. An interrupt is generated. IFN Interrupt FuNction IFN = 1, the serial interrupt is generated at the end of telegram IFN = 0, the serial interrupt is generated when the SRDY goes low (i.e., buffer becomes empty/full in transmit/receive mode) SRDY Serial interface buffer ReaDY status flag SRDY = 1, in receive mode: receive buffer empty in transmit mode: transmit buffer full SRDY = 0, in receive mode: receive buffer full in transmit mode: transmit buffer empty ACT Transmission ACTive status flag ACT = 1, transmission is active, i.e., serial data transfer. Stop or start conditions are currently in progress. ACT = 0, transmission is inactive Serial Transmit Buffer (STB) – Byte Write Primary register address: ’9’hex STB First write cycle Bit 3 Bit 2 Bit 1 Bit 0 Reset value: xxxxb Second write cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: xxxxb The STB is the transmit buffer of the SSI. The SSI transfers the transmit buffer into the shift register and starts shifting with the most significant bit. |
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