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DSP56857 Datasheet(PDF) 144 Page - Freescale Semiconductor, Inc |
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DSP56857 Datasheet(HTML) 144 Page - Freescale Semiconductor, Inc |
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144 / 662 page  Timing Specifications 5685X Digital Signal Controller User Manual, Rev. 4 5-18 Freescale Semiconductor Figure 5-12. External Write Cycle Note: When WWS = 0 the timing of the WR strobe is generated from different clock edges than when it is set to some other value. This change in timing allows the possibility of single cycle write operation, but reduces the pulse width of WR to one quarter clock. This may make it difficult to meet write timing requirements for most devices when operating at normal clock rates. tCWH tCWH tCSV tWHZ tAV tAV tWAC IDLE Write (WWS = 0) Write (WWS = 0) IDLE tC tWRH tAVW tDH tDW tWRL tDH tDW int_sys_clk(core) int_delay_SEMI_clk A[23:0] RD = OE D[16:0] CS2 WR tWC tWDE tWDO tCWL tAVW tWHZ tWDO tWDE tCWL tAVW tCSL tCSV Write (WWS = 0) |
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