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DSP56857 Datasheet(PDF) 147 Page - Freescale Semiconductor, Inc |
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DSP56857 Datasheet(HTML) 147 Page - Freescale Semiconductor, Inc |
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147 / 662 page  Timing Specifications External Memory Interface (EMI), Rev. 4 Freescale Semiconductor 5-21 Figure 5-15. External Write Cycle with WWS = 0, WWSH = 1, WWSS = 0 5.7.2.3 WWS > 0 Although most memory devices require a zero setup and hold time, there are some peripheral devices where a setup/hold time is required. The WWSS and WWSH field of the CSTC register provides the ability to allow for a write setup and/or hold time requirement as shown in Figure 5-16 and Figure 5-17 respectively. tCWH tCWL tCWH tCWL tCSV tCSV tWHZ tWDO tWDE tWHZ tWDE tWDO tAV tAV tWAC tCSL tWC IDLE Write (WWS=0, Write (WWS=0,WWSH=1) IDLE tC Write (WWS=0,WWSH=1) tAVW tWRH tDH tDW tAVW tWRL tDH tDW tAVW int_sys_clk(core) int_delay_SEMI_clk A[23:0] RD = OE D[16:0] CS2 WR WWSH=1) Time added to Figure 5-12 by setting WWSS = 1 |
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