HD64F2145 datasheet(342/829 Pages) RENESAS

342 / 829 page

Rev. 2.0, 08/02, page 302 of 788

Bit

Bit Name

Initial Value

R/W

Description

HFINV

VFINV

HIINV

VIINV

R/W

Input Synchronization Signal Inversion

These bits select inversion of the input phase of the

spare horizontal synchronization signal (HFBACKI),

the spare vertical synchronization signal (VFBACKI),

the horizontal synchronization signal (HSYNCI),

composite synchronization signal (CSYNCI), and the

vertical synchronization signal (VSYNCI).

• HFINV

0: The HFBACKI pin state is used directly as the

HFBACKI input

1: The HFBACKI pin state is inverted before use as

the HFBACKI input

• VFINV

0: The VFBACKI pin state is used directly as the

VFBACKI input

1: The VFBACKI pin state is inverted before use as the

VFBACKI input

• HIINV

0: The HSYNCI and CSYNCI pin states are used

directly as the HSYNCI and CSYNCI inputs

1: The HSYNCI and CSYNCI pin states are inverted

before use as the HSYNCI and CSYNCI inputs

• VIINV

0: The VSYNCI pin state is used directly as the

VSYNCI input

1: The VSYNCI pin state is inverted before use as the

VSYNCI input

Legend

Don’t care

Table 13.2

Synchronization Signal Connection Enable

Bit 5

Description

SCONE

Mode

FTIA

FTIB

FTIC

FTID

TMCI1 TMRI1

Normal connection (Initial value)

FTIA

input

FTIB

input

FTIC

input

FTID

input

TMCI1

input

TMRI1

input

Synchronization signal

connection mode

IVI

signal

TMO1

signal

VFBACKI

input

IHI

signal

IHI

signal

IVI

inverse

signal

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