HD64F2145 datasheet(343/829 Pages) RENESAS

343 / 829 page

Rev. 2.0, 08/02, page 303 of 788

13.3.2

Timer Connection Register O (TCONRO)

TCONRO controls output signal output, phase inversion, etc.

Bit

Bit Name

Initial Value

R/W

Description

HOE

VOE

CLOE

CBOE

R/W

Output Enable

These bits control enabling/disabling of output of

horizontal synchronization signal (HSYNCO), vertical

synchronization signal (VSYNCO), clamp waveform

(CLAMPO), and blanking waveform (CBLANK). When

output is disabled, the state of the relevant pin is

determined by port DR and DDR, FRT, TMR, and

PWM settings.

Output enabling/disabling control does not affect the

port, FRT, or TMR input functions, but some FRT and

TMR input signal sources are determined by the

SCONE bit in TCONRI.

HOE:

0: The P44/TMO1/HIRQ1/HSYNCO pin functions as

the P44/TMO1/HIRQ1 pin

1: The P44/TMO1/HIRQ1/HSYNCO pin functions as

the HSYNCO pin

VOE:

0: The P61/FTOA/CIN1/

.,14/VSYNCO pin functions

as the P61/FTOA/CIN1/

.,14 pin

1: The P61/FTOA/CIN1/

.,14/VSYNCO pin functions

as the VSYNCO pin

CLOE:

0: The P64/FTIC/CIN4/

.,17/CLAMPO pin functions as

the P64/FTIC/CIN4/

.,17 pin

1: The P64/FTIC/CIN4/

.,17/CLAMPO pin functions as

the CLAMPO pin

CBOE:

0: The P27/A15/PW15/CBLANK pin functions as the

P27/A15/PW15 pin

In mode 1:

1: The P27/A15/PW15/CBLANK pin functions as the

A15 pin

In modes 2 and 3:

1: The P27/A15/PW15/CBLANK pin functions as the

CBLANK pin

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