HD64F2145 datasheet(121/829 Pages) RENESAS

121 / 829 page

Rev. 2.0, 08/02, page 81 of 788

4.3

Reset

A reset has the highest exception priority. When the

5(6 pin goes low, all processing halts and

this LSI enters the reset. To ensure that this LSI is reset, hold the

5(6 pin low for at least 20 ms at

power-on. To reset the chip during operation, hold the

5(6 pin low for at least 20 states. A reset

initializes the internal state of the CPU and the registers of on-chip peripheral modules. The chip

can also be reset by overflow of the watchdog timer. For details, see section 14, Watchdog Timer

(WDT).

4.3.1

Reset Exception Handling

When the

5(6 pin goes high after being held low for the necessary time, this LSI starts reset

exception handling as follows:

1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized

and the I bit is set to 1 in CCR.

2. The reset exception handling vector address is read and transferred to the PC, and program

execution starts from the address indicated by the PC.

Figure 4.1 shows an example of the reset sequence.

Internal address bus

Internal read signal

Internal write signal

Internal data bus

Vector

fetch

(1) Reset exception handling vector address ((1) = H'0000)

(2) Start address (contents of reset exception handling vector address)

(3) Start address ((3) = (2))

(4) First program instruction

(1)

(3)

High

Internal

processing

Prefetch of first program

instruction

(2)

(4)

Figure 4.1 Reset Sequence (Mode 3)

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