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HD64F2145 Datasheet(PDF) 259 Page - Renesas Technology Corp |
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HD64F2145 Datasheet(HTML) 259 Page - Renesas Technology Corp |
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259 / 829 page  Rev. 2.0, 08/02, page 219 of 788 9.2 Input/Output Pin Table 9.1 shows the PWM output pins. Table 9.1 Pin Configuration Name Abbreviation I/O Function PWM output 15 to 0 PW15 to PW0 Output PWM timer pulse output 15 to 0 9.3 Register Descriptions The PWM has the following registers. To access PCSR, the FLSHE bit in the serial timer control register (STCR) must be cleared to 0. For details on the serial timer control register (STCR), see section 3.2.3, Serial Timer Control Register (STCR). • PWM register select (PWSL) • PWM data registers 0 to 15 (PWDR0 to PWDR15) • PWM data polarity register A (PWDPRA) • PWM data polarity register B (PWDPRB) • PWM output enable register A (PWOERA) • PWM output enable register B (PWOERB) • Peripheral clock select register (PCSR) |
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